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Fix exc wiring (not working yet)
This commit is contained in:
Sven Stucki
parent
c68a098059
commit
c28ca4444a
5 changed files with 50 additions and 32 deletions
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@ -43,7 +43,7 @@ module riscv_controller
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// decoder related signals
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output logic deassert_we_o, // deassert write enable for next instruction
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input logic illegal_insn_i, // decoder encountered an invalid instruction // TODO: Remove?
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input logic illegal_insn_i, // decoder encountered an invalid instruction
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input logic eret_insn_i, // decoder encountered an eret instruction
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input logic pipe_flush_i, // decoder wants to do a pipe flush
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@ -82,6 +82,9 @@ module riscv_controller
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// TODO
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input logic trap_hit_i, // a trap was hit, so we have to flush EX and WB
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output logic save_pc_if_o,
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output logic save_pc_id_o,
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// Debug Unit Signals
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input logic dbg_stall_i, // Pipeline stall is requested
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input logic dbg_set_npc_i, // Change PC to value from debug unit
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@ -164,21 +167,23 @@ module riscv_controller
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always_comb
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begin
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// Default values
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instr_req_o = 1'b1;
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instr_req_o = 1'b1;
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exc_ack_o = 1'b0;
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exc_ack_o = 1'b0;
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save_pc_if_o = 1'b0;
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save_pc_id_o = 1'b0;
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pc_mux_sel_o = `PC_BOOT;
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pc_set_o = 1'b0;
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pc_mux_sel_o = `PC_BOOT;
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pc_set_o = 1'b0;
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ctrl_fsm_ns = ctrl_fsm_cs;
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ctrl_fsm_ns = ctrl_fsm_cs;
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core_busy_o = 1'b1;
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is_decoding_o = 1'b0;
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core_busy_o = 1'b1;
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is_decoding_o = 1'b0;
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halt_if_o = 1'b0;
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halt_id_o = 1'b0;
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dbg_trap_o = 1'b0;
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halt_if_o = 1'b0;
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halt_id_o = 1'b0;
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dbg_trap_o = 1'b0;
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unique case (ctrl_fsm_cs)
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// We were just reset, wait for fetch_enable
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@ -272,6 +277,12 @@ module riscv_controller
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pc_set_o = 1'b1;
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exc_ack_o = 1'b1;
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// TODO: Check
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if (jump_in_dec_i == `BRANCH_JALR || jump_in_dec_i == `BRANCH_JAL)
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save_pc_if_o = 1'b1;
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else
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save_pc_id_o = 1'b1;
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// we don't have to change our current state here as the prefetch
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// buffer is automatically invalidated, thus the next instruction
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// that is served to the ID stage is the one of the jump to the
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@ -35,7 +35,8 @@ module riscv_decoder
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output logic illegal_insn_o, // illegal instruction encountered
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output logic trap_insn_o, // trap instruction encountered
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output logic eret_insn_o, // trap instruction encountered
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output logic eret_insn_o, // return from exception instruction encountered
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output logic ecall_insn_o, // environment call (syscall) instruction encountered
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output logic pipe_flush_o, // pipeline flush is requested
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output logic rega_used_o, // rs1 is used by current instruction
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@ -159,6 +160,7 @@ module riscv_decoder
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illegal_insn_o = 1'b0;
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trap_insn = 1'b0;
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eret_insn = 1'b0;
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ecall_insn_o = 1'b0;
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pipe_flush = 1'b0;
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rega_used_o = 1'b0;
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@ -512,7 +514,7 @@ module riscv_decoder
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32'h00_00_00_73: // ECALL
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begin
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// environment (system) call
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// TODO: Handle in controller
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ecall_insn_o = 1'b1;
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end
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32'h00_10_00_73: // ebreak
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31
id_stage.sv
31
id_stage.sv
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@ -124,7 +124,7 @@ module riscv_id_stage
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input logic irq_enable_i,
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output logic [5:0] exc_cause_o,
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input logic save_exc_cause_o,
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output logic save_exc_cause_o,
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output logic save_pc_if_o,
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output logic save_pc_id_o,
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@ -166,6 +166,7 @@ module riscv_id_stage
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logic illegal_insn_dec;
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logic trap_insn;
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logic eret_insn_dec;
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logic ecall_insn_dec;
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logic pipe_flush_dec;
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logic rega_used_dec;
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@ -193,15 +194,13 @@ module riscv_id_stage
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logic [31:0] jump_target; // calculated jump target (-> EX -> IF)
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logic exc_pc_sel;
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logic irq_present;
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// Signals running between controller and exception controller
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logic illegal_insn;
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logic exc_req, exc_ack; // handshake
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logic trap_hit;
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logic clear_isr_running;
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logic exc_pipe_flush;
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assign trap_hit = 1'b0; // TODO: Fix
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// Register file interface
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logic [4:0] regfile_addr_ra_id;
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@ -248,7 +247,6 @@ module riscv_id_stage
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logic [1:0] hwloop_regid;
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logic [2:0] hwloop_we;
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logic hwloop_jump;
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logic hwloop_enable;
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logic hwloop_start_mux_sel;
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logic hwloop_end_mux_sel;
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logic hwloop_cnt_mux_sel;
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@ -535,6 +533,7 @@ module riscv_id_stage
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.illegal_insn_o ( illegal_insn_dec ),
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.trap_insn_o ( trap_insn ),
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.eret_insn_o ( eret_insn_dec ),
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.ecall_insn_o ( ecall_insn_dec ),
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.pipe_flush_o ( pipe_flush_dec ),
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.rega_used_o ( rega_used_dec ),
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@ -647,6 +646,9 @@ module riscv_id_stage
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.exc_ack_o ( exc_ack ),
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.trap_hit_i ( trap_hit ),
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.save_pc_id_o ( save_pc_id_o ),
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.save_pc_if_o ( save_pc_if_o ),
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// Debug Unit Signals
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.dbg_stall_i ( dbg_stall_i ),
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.dbg_set_npc_i ( dbg_set_npc_i ),
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@ -702,8 +704,8 @@ module riscv_id_stage
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.rst_n ( rst_n ),
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// to controller
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.req_o ( exc_req_o ),
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.ack_i ( exc_ack_i ),
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.req_o ( exc_req ),
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.ack_i ( exc_ack ),
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// to IF stage
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.pc_mux_o ( exc_pc_mux_o ),
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@ -713,11 +715,12 @@ module riscv_id_stage
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.irq_i ( irq_i ),
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.irq_enable_i ( irq_enable_i ),
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.illegal_insn_i ( illegal_insn ),
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.ecall_insn_i ( ecall_insn ),
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.eret_insn_i ( eret_insn ),
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.illegal_insn_i ( illegal_insn_dec ),
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.ecall_insn_i ( ecall_insn_dec ),
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.eret_insn_i ( eret_insn_dec ),
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.cause_o ( exc_cause_o )
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.cause_o ( exc_cause_o ),
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.save_cause_o ( save_exc_cause_o )
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);
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@ -733,7 +736,7 @@ module riscv_id_stage
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riscv_hwloop_controller hwloop_controller_i
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(
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// from ID stage
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.enable_i ( hwloop_enable ),
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.enable_i ( 1'b1 ),
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.current_pc_i ( current_pc_if_i ),
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// to IF stage/controller
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@ -122,7 +122,6 @@ module riscv_if_stage
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logic [31:0] instr_rdata_int;
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logic [31:0] exc_pc;
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logic [31:0] irq_pc;
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// output data and PC mux
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@ -90,6 +90,7 @@ module riscv_core
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logic pc_set;
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logic [2:0] pc_mux_sel_id; // Mux selector for next PC
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logic [1:0] exc_pc_mux_id; // Mux selector for exception PC
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logic [4:0] exc_vec_pc_mux_id; // Mux selector for vectorized IR lines
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logic branch_done; // Branch already done
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@ -253,10 +254,11 @@ module riscv_core
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.current_pc_id_o ( current_pc_id ), // current pc in ID stage
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// control signals
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.pc_set_i ( pc_set ),
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.exception_pc_reg_i ( epcr ), // exception return address
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.pc_mux_sel_i ( pc_mux_sel_id ), // sel for pc multiplexer
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.exc_pc_mux_i ( exc_pc_mux_id ), // selector for exception multiplexer
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.pc_set_i ( pc_set ),
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.exception_pc_reg_i ( epcr ), // Exception PC register
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.pc_mux_sel_i ( pc_mux_sel_id ), // sel for pc multiplexer
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.exc_pc_mux_i ( exc_pc_mux_id ),
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.exc_vec_pc_mux_i ( exc_vec_pc_mux_id ),
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.branch_done_o ( branch_done ),
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@ -316,6 +318,7 @@ module riscv_core
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.pc_set_o ( pc_set ),
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.pc_mux_sel_o ( pc_mux_sel_id ),
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.exc_pc_mux_o ( exc_pc_mux_id ),
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.exc_vec_pc_mux_o ( exc_vec_pc_mux_id ),
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.branch_done_i ( branch_done ),
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