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CSRs: replace _n suffix of register signals by _d
This commit is contained in:
Pirmin Vogel
parent
b1df836940
commit
c437008310
1 changed files with 70 additions and 70 deletions
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@ -149,22 +149,22 @@ module ibex_cs_registers #(
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logic [31:0] exception_pc;
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// CSRs
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Status_t mstatus_q, mstatus_n;
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logic [31:0] mscratch_q, mscratch_n;
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logic [31:0] mepc_q, mepc_n;
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logic [5:0] mcause_q, mcause_n;
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logic [31:0] mtval_q, mtval_n;
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Dcsr_t dcsr_q, dcsr_n;
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logic [31:0] depc_q, depc_n;
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logic [31:0] dscratch0_q, dscratch0_n;
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logic [31:0] dscratch1_q, dscratch1_n;
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Status_t mstatus_q, mstatus_d;
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logic [31:0] mscratch_q, mscratch_d;
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logic [31:0] mepc_q, mepc_d;
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logic [5:0] mcause_q, mcause_d;
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logic [31:0] mtval_q, mtval_d;
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Dcsr_t dcsr_q, dcsr_d;
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logic [31:0] depc_q, depc_d;
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logic [31:0] dscratch0_q, dscratch0_d;
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logic [31:0] dscratch1_q, dscratch1_d;
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// Hardware performance monitor signals
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logic [31:0] mcountinhibit_n, mcountinhibit_q, mcountinhibit;
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logic [31:0] mcountinhibit_d, mcountinhibit_q, mcountinhibit;
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logic [31:0] mcountinhibit_force;
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logic mcountinhibit_we;
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logic [63:0] mhpmcounter_mask [32];
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logic [63:0] mhpmcounter_n [32];
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logic [63:0] mhpmcounter_d [32];
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logic [63:0] mhpmcounter_q [32];
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logic [31:0] mhpmcounter_we;
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logic [31:0] mhpmcounterh_we;
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@ -284,15 +284,15 @@ module ibex_cs_registers #(
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always_comb begin
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exception_pc = pc_id_i;
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mstatus_n = mstatus_q;
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mscratch_n = mscratch_q;
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mepc_n = mepc_q;
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mcause_n = mcause_q;
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mtval_n = mtval_q;
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dcsr_n = dcsr_q;
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depc_n = depc_q;
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dscratch0_n = dscratch0_q;
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dscratch1_n = dscratch1_q;
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mstatus_d = mstatus_q;
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mscratch_d = mscratch_q;
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mepc_d = mepc_q;
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mcause_d = mcause_q;
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mtval_d = mtval_q;
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dcsr_d = dcsr_q;
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depc_d = depc_q;
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dscratch0_d = dscratch0_q;
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dscratch1_d = dscratch1_q;
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mcountinhibit_we = 1'b0;
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mhpmcounter_we = '0;
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mhpmcounterh_we = '0;
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@ -301,7 +301,7 @@ module ibex_cs_registers #(
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// mstatus: IE bit
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CSR_MSTATUS: begin
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if (csr_we_int) begin
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mstatus_n = '{
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mstatus_d = '{
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mie: csr_wdata_int[`MSTATUS_MIE_BITS],
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mpie: csr_wdata_int[`MSTATUS_MPIE_BITS],
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mpp: PRIV_LVL_M
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@ -309,52 +309,52 @@ module ibex_cs_registers #(
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end
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end
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CSR_MSCRATCH: if (csr_we_int) mscratch_n = csr_wdata_int;
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CSR_MSCRATCH: if (csr_we_int) mscratch_d = csr_wdata_int;
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// mepc: exception program counter
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CSR_MEPC: if (csr_we_int) mepc_n = {csr_wdata_int[31:1], 1'b0};
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CSR_MEPC: if (csr_we_int) mepc_d = {csr_wdata_int[31:1], 1'b0};
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// mcause
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CSR_MCAUSE: if (csr_we_int) mcause_n = {csr_wdata_int[31], csr_wdata_int[4:0]};
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CSR_MCAUSE: if (csr_we_int) mcause_d = {csr_wdata_int[31], csr_wdata_int[4:0]};
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// mtval: trap value
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CSR_MTVAL: if (csr_we_int) mtval_n = csr_wdata_int;
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CSR_MTVAL: if (csr_we_int) mtval_d = csr_wdata_int;
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CSR_DCSR: begin
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if (csr_we_int) begin
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dcsr_n = csr_wdata_int;
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dcsr_n.xdebugver = XDEBUGVER_STD;
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dcsr_n.prv = PRIV_LVL_M; // only M-mode is supported
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dcsr_d = csr_wdata_int;
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dcsr_d.xdebugver = XDEBUGVER_STD;
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dcsr_d.prv = PRIV_LVL_M; // only M-mode is supported
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// currently not supported:
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dcsr_n.nmip = 1'b0;
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dcsr_n.mprven = 1'b0;
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dcsr_n.stopcount = 1'b0;
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dcsr_n.stoptime = 1'b0;
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dcsr_d.nmip = 1'b0;
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dcsr_d.mprven = 1'b0;
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dcsr_d.stopcount = 1'b0;
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dcsr_d.stoptime = 1'b0;
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// forced to be zero
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dcsr_n.zero0 = 1'b0;
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dcsr_n.zero1 = 1'b0;
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dcsr_n.zero2 = 12'h0;
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dcsr_d.zero0 = 1'b0;
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dcsr_d.zero1 = 1'b0;
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dcsr_d.zero2 = 12'h0;
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end
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end
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CSR_DPC: begin
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// Only valid PC addresses are allowed (half-word aligned with C ext.)
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if (csr_we_int && csr_wdata_int[0] == 1'b0) begin
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depc_n = csr_wdata_int;
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depc_d = csr_wdata_int;
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end
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end
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CSR_DSCRATCH0: begin
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if (csr_we_int) begin
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dscratch0_n = csr_wdata_int;
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dscratch0_d = csr_wdata_int;
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end
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end
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CSR_DSCRATCH1: begin
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if (csr_we_int) begin
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dscratch1_n = csr_wdata_int;
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dscratch1_d = csr_wdata_int;
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end
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end
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@ -417,27 +417,27 @@ module ibex_cs_registers #(
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if (debug_csr_save_i) begin
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// all interrupts are masked, don't update cause, epc, tval dpc and
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// mpstatus
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dcsr_n.prv = PRIV_LVL_M;
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dcsr_n.cause = debug_cause_i;
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depc_n = exception_pc;
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dcsr_d.prv = PRIV_LVL_M;
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dcsr_d.cause = debug_cause_i;
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depc_d = exception_pc;
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end else begin
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mstatus_n.mpie = mstatus_q.mie;
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mstatus_n.mie = 1'b0;
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mstatus_n.mpp = PRIV_LVL_M;
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mepc_n = exception_pc;
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mcause_n = {csr_mcause_i};
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mtval_n = csr_mtval_i;
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mstatus_d.mpie = mstatus_q.mie;
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mstatus_d.mie = 1'b0;
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mstatus_d.mpp = PRIV_LVL_M;
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mepc_d = exception_pc;
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mcause_d = {csr_mcause_i};
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mtval_d = csr_mtval_i;
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end
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end //csr_save_cause_i
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csr_restore_mret_i: begin //MRET
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mstatus_n.mie = mstatus_q.mpie;
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mstatus_n.mpie = 1'b1;
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mstatus_d.mie = mstatus_q.mpie;
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mstatus_d.mpie = 1'b1;
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end //csr_restore_mret_i
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csr_restore_dret_i: begin //DRET
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mstatus_n.mie = mstatus_q.mpie;
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mstatus_n.mpie = 1'b1;
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mstatus_d.mie = mstatus_q.mpie;
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mstatus_d.mpie = 1'b1;
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end //csr_restore_dret_i
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default:;
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@ -500,18 +500,18 @@ module ibex_cs_registers #(
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end else begin
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// update CSRs
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mstatus_q <= '{
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mie: mstatus_n.mie,
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mpie: mstatus_n.mpie,
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mie: mstatus_d.mie,
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mpie: mstatus_d.mpie,
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mpp: PRIV_LVL_M
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};
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mscratch_q <= mscratch_n;
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mepc_q <= mepc_n;
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mcause_q <= mcause_n;
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mtval_q <= mtval_n;
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dcsr_q <= dcsr_n;
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depc_q <= depc_n;
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dscratch0_q <= dscratch0_n;
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dscratch1_q <= dscratch1_n;
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mscratch_q <= mscratch_d;
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mepc_q <= mepc_d;
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mcause_q <= mcause_d;
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mtval_q <= mtval_d;
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dcsr_q <= dcsr_d;
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depc_q <= depc_d;
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dscratch0_q <= dscratch0_d;
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dscratch1_q <= dscratch1_d;
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end
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end
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@ -522,12 +522,12 @@ module ibex_cs_registers #(
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// update enable signals
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always_comb begin : mcountinhibit_update
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if (mcountinhibit_we == 1'b1) begin
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mcountinhibit_n = csr_wdata_int;
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mcountinhibit_d = csr_wdata_int;
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end else begin
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mcountinhibit_n = mcountinhibit_q;
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mcountinhibit_d = mcountinhibit_q;
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end
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// bit 1 must always be 0
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mcountinhibit_n[1] = 1'b0;
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mcountinhibit_d[1] = 1'b0;
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end
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assign mcountinhibit_force = {{29-MHPMCounterNum{1'b1}}, {MHPMCounterNum{1'b0}}, 3'b000};
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@ -593,20 +593,20 @@ module ibex_cs_registers #(
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// update
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always_comb begin : mhpmcounter_update
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mhpmcounter_n = mhpmcounter_q;
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mhpmcounter_d = mhpmcounter_q;
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for (int i=0; i<32; i++) begin : gen_mhpmcounter_update
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// increment
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if (mhpmcounter_incr[i] & ~mcountinhibit[i]) begin
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mhpmcounter_n[i] = mhpmcounter_mask[i] & (mhpmcounter_q[i] + 64'h1);
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mhpmcounter_d[i] = mhpmcounter_mask[i] & (mhpmcounter_q[i] + 64'h1);
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end
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// write
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if (mhpmcounter_we[i]) begin
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mhpmcounter_n[i][31: 0] = mhpmcounter_mask[i][31: 0] & csr_wdata_int;
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mhpmcounter_d[i][31: 0] = mhpmcounter_mask[i][31: 0] & csr_wdata_int;
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end else if (mhpmcounterh_we[i]) begin
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mhpmcounter_n[i][63:32] = mhpmcounter_mask[i][63:32] & csr_wdata_int;
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mhpmcounter_d[i][63:32] = mhpmcounter_mask[i][63:32] & csr_wdata_int;
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end
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end
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end
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@ -619,8 +619,8 @@ module ibex_cs_registers #(
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mhpmcounter_q[i] <= '0;
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end
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end else begin
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mhpmcounter_q <= mhpmcounter_n;
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mcountinhibit_q <= mcountinhibit_n;
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mhpmcounter_q <= mhpmcounter_d;
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mcountinhibit_q <= mcountinhibit_d;
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end
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end
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