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Make sure that the correct register is accessed in ASIC for PCCRs

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This commit is contained in:
Andreas Traber 2015-12-07 17:01:27 +01:00
parent ac384a23d4
commit c73c6acc85
1 changed files with 6 additions and 1 deletions
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7
cs_registers.sv
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@ -321,8 +321,13 @@ module riscv_cs_registers
is_pccr = 1'b1;
pccr_index = csr_addr_i[4:0];
`ifndef PULP_FPGA_EMUL
perf_rdata = PCCR_q[csr_addr_i[4:0]];
`elsif SYNTHESIS
perf_rdata = PCCR_q[0];
`else
perf_rdata = PCCR_q[csr_addr_i[4:0]];
`endif
end
end
end