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[dv] Fix race condition in cs_registers testbench
The `driver_tick` DPI call drove inputs directly but was being scheduled in an undefined order with other always_ff blocks. This results in a race condition where some always_ff blocks see old inputs and others see new in the same clock tick. Instead use values from `driver_tick` to perform NBA updates and avoid the race condition.
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1 changed files with 24 additions and 5 deletions
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@ -33,6 +33,11 @@ module tb_cs_registers #(
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logic illegal_csr_insn_o;
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logic csr_access_d;
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ibex_pkg::csr_num_e csr_addr_d;
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logic [31:0] csr_wdata_d;
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ibex_pkg::csr_op_e csr_op_d;
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logic csr_op_en_d;
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//-----------------
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// Reset generation
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//-----------------
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@ -121,12 +126,26 @@ module tb_cs_registers #(
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csr_addr_i,
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csr_wdata_i,
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csr_rdata_o);
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reg_dpi::driver_tick("reg_driver",
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csr_access_i,
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csr_op_i,
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csr_op_en_i,
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csr_addr_i,
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csr_wdata_i);
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csr_access_d,
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csr_op_d,
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csr_op_en_d,
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csr_addr_d,
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csr_wdata_d);
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// Use NBA to drive inputs to ensure correct scheduling.
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// This always_ff block will be executed on the positive edge of the clock with undefined order
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// vs all other always_ff triggered on the positive edge of the clock. If `driver_tick` drives
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// the inputs directly some of the always_ff blocks will see the old version of the inputs and
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// others will see the new version depending on scheduling order. This schedules all the inputs
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// to be NBA updates to avoid the race condition (in effect acting like any other always_ff
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// block with the _d values being computed via DPI rather than combinational logic).
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csr_access_i <= csr_access_d;
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csr_addr_i <= csr_addr_d;
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csr_wdata_i <= csr_wdata_d;
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csr_op_i <= csr_op_d;
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csr_op_en_i <= csr_op_en_d;
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end
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endmodule
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