Use 'or' instead of ',' inside '@( )' statements

rtl/ibex_controller.sv

@@ -498,7 +498,7 @@ module ibex_controller (
   assign operand_a_fw_mux_sel_o = data_misaligned_i ? SEL_MISALIGNED : SEL_REGFILE;
 
   // update registers
-  always_ff @(posedge clk_i, negedge rst_ni) begin : UPDATE_REGS
+  always_ff @(posedge clk_i or negedge rst_ni) begin : UPDATE_REGS
     if (!rst_ni) begin
       ctrl_fsm_cs <= RESET;
       //jump_done_q <= 1'b0;

rtl/ibex_core.sv

@@ -197,7 +197,7 @@ module ibex_core #(
   // interface to finish loading instructions
   assign core_busy_int = if_busy | ctrl_busy | lsu_busy;
 
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       core_busy_q <= 1'b0;
     end else begin

rtl/ibex_cs_registers.sv

@@ -359,7 +359,7 @@ module ibex_cs_registers #(
   assign debug_ebreakm_o      = dcsr_q.ebreakm;
 
   // actual registers
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       mstatus_q  <= '{
               mie:  1'b0,
@@ -532,7 +532,7 @@ module ibex_cs_registers #(
   end
 
   // Performance Counter Registers
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       PCER_q <= '0;
       PCMR_q <= 2'h3;

rtl/ibex_fetch_fifo.sv

@@ -182,7 +182,7 @@ module ibex_fetch_fifo (
   // registers //
   ///////////////
 
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       addr_q    <= '{default: '0};
       rdata_q   <= '{default: '0};

rtl/ibex_id_stage.sv

@@ -541,7 +541,7 @@ module ibex_id_stage #(
   ////////////////////////////////
   // ID-EX/WB Pipeline Register //
   ////////////////////////////////
-  always_ff @(posedge clk_i, negedge rst_ni) begin : EX_WB_Pipeline_Register
+  always_ff @(posedge clk_i or negedge rst_ni) begin : EX_WB_Pipeline_Register
     if (!rst_ni) begin
       id_wb_fsm_cs  <= IDLE;
       branch_set_q  <= 1'b0;

rtl/ibex_if_stage.sv

@@ -155,7 +155,7 @@ module ibex_if_stage #(
 
 
   // offset initialization state
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       offset_in_init_q <= 1'b1;
     end else begin
@@ -219,7 +219,7 @@ module ibex_if_stage #(
   );
 
   // IF-ID pipeline registers, frozen when the ID stage is stalled
-  always_ff @(posedge clk_i, negedge rst_ni) begin : IF_ID_PIPE_REGISTERS
+  always_ff @(posedge clk_i or negedge rst_ni) begin : IF_ID_PIPE_REGISTERS
     if (!rst_ni) begin
       instr_valid_id_o      <= 1'b0;
       instr_rdata_id_o      <= '0;

rtl/ibex_int_controller.sv

@@ -50,7 +50,7 @@ module ibex_int_controller (
   assign irq_req_ctrl_o = exc_ctrl_cs == IRQ_PENDING;
   assign irq_id_ctrl_o  = irq_id_q;
 
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       irq_id_q    <= '0;
       exc_ctrl_cs <= IDLE;

rtl/ibex_load_store_unit.sv

@@ -157,7 +157,7 @@ module ibex_load_store_unit (
 
 
   // FF for rdata alignment and sign-extension
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       data_type_q     <= 2'h0;
       rdata_offset_q  <= 2'h0;
@@ -277,7 +277,7 @@ module ibex_load_store_unit (
 
 
 
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       CS            <= IDLE;
       rdata_q       <= '0;

rtl/ibex_prefetch_buffer.sv

@@ -210,7 +210,7 @@ module ibex_prefetch_buffer (
   // Registers //
   ///////////////
 
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       CS              <= IDLE;
       instr_addr_q    <= '0;

rtl/ibex_register_file.sv

@@ -89,7 +89,7 @@ module ibex_register_file #(
   );
 
   // use clk_int here, since otherwise we don't want to write anything anyway
-  always_ff @(posedge clk_int, negedge rst_ni) begin : sample_waddr
+  always_ff @(posedge clk_int or negedge rst_ni) begin : sample_waddr
     if (!rst_ni) begin
       wdata_a_q   <= '0;
     end else begin

rtl/ibex_register_file_ff.sv

@@ -65,7 +65,7 @@ module ibex_register_file #(
   end
 
   // loop from 1 to NUM_WORDS-1 as R0 is nil
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       rf_reg_tmp <= '{default:'0};
     end else begin

rtl/ibex_tracer.sv

@@ -291,7 +291,7 @@ module ibex_tracer #(
   mailbox #(instr_trace_t) instr_wb = new ();
 
   // cycle counter
-  always_ff @(posedge clk_i, negedge rst_ni) begin
+  always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       cycles = 0;
     end else begin