mirror of
https://github.com/lowRISC/ibex.git
synced 2025-04-23 21:39:13 -04:00
Re-indent sim.py
This should have no functional change: it just indents the code with 4-space indents and wraps any long lines.
This commit is contained in:
Rupert Swarbrick
Rupert Swarbrick
parent
32ba3cd92e
commit
ca61654261
1 changed files with 201 additions and 180 deletions
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@ -34,189 +34,207 @@ from instr_trace_compare import *
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def process_cmd(keyword, cmd, opts, enable):
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""" Process the compile and simulation command
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""" Process the compile and simulation command
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Args:
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keyword : Keyword to search
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cmd : Command to be processed
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opts : Options to replace the keyword
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enable : Option enable/disable
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Args:
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keyword : Keyword to search
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cmd : Command to be processed
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opts : Options to replace the keyword
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enable : Option enable/disable
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Returns:
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Processed command
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"""
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if enable == "1":
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return re.sub(keyword, opts.rstrip(), cmd)
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else:
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return re.sub(keyword, "", cmd)
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Returns:
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Processed command
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"""
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if enable == "1":
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return re.sub(keyword, opts.rstrip(), cmd)
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else:
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return re.sub(keyword, "", cmd)
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def get_simulator_cmd(simulator, simulator_yaml, en_cov, en_wave):
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""" Setup the compile and simulation command for the generator
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""" Setup the compile and simulation command for the generator
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Args:
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simulator : RTL simulator used to run instruction generator
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simulator_yaml : RTL simulator configuration file in YAML format
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en_cov : Enable coverage dump
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en_wave : Enable waveform
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Args:
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simulator : RTL simulator used to run instruction generator
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simulator_yaml : RTL simulator configuration file in YAML format
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en_cov : Enable coverage dump
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en_wave : Enable waveform
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Returns:
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compile_cmd : RTL simulator command to compile the instruction generator
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sim_cmd : RTL simulator command to run the instruction generator
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"""
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logging.info("Processing simulator setup file : %s" % simulator_yaml)
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yaml_data = read_yaml(simulator_yaml)
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# Search for matched simulator
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for entry in yaml_data:
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if entry['tool'] == simulator:
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logging.info("Found matching simulator: %s" % entry['tool'])
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compile_cmd = entry['compile']['cmd']
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for i in range(len(compile_cmd)):
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if 'cov_opts' in entry['compile']:
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compile_cmd[i] = process_cmd("<cov_opts>", compile_cmd[i],
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entry['compile']['cov_opts'], en_cov)
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if 'wave_opts' in entry['compile']:
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compile_cmd[i] = process_cmd("<wave_opts>", compile_cmd[i],
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entry['compile']['wave_opts'], en_wave)
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sim_cmd = entry['sim']['cmd']
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if 'cov_opts' in entry['sim']:
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sim_cmd = process_cmd("<cov_opts>", sim_cmd, entry['sim']['cov_opts'], en_cov)
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if 'wave_opts' in entry['sim']:
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sim_cmd = process_cmd("<wave_opts>", sim_cmd, entry['sim']['wave_opts'], en_wave)
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if 'env_var' in entry:
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for env_var in entry['env_var'].split(','):
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for i in range(len(compile_cmd)):
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compile_cmd[i] = re.sub("<"+env_var+">", get_env_var(env_var), compile_cmd[i])
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sim_cmd = re.sub("<"+env_var+">", get_env_var(env_var), sim_cmd)
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return compile_cmd, sim_cmd
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logging.error("Cannot find RTL simulator %0s" % simulator)
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sys.exit(RET_FAIL)
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Returns:
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compile_cmd : RTL simulator command to compile instruction generator
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sim_cmd : RTL simulator command to run the instruction generator
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"""
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logging.info("Processing simulator setup file : %s" % simulator_yaml)
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yaml_data = read_yaml(simulator_yaml)
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# Search for matched simulator
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for entry in yaml_data:
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if entry['tool'] != simulator:
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continue
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logging.info("Found matching simulator: %s" % entry['tool'])
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compile_cmd = entry['compile']['cmd']
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for i in range(len(compile_cmd)):
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if 'cov_opts' in entry['compile']:
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compile_cmd[i] = process_cmd("<cov_opts>", compile_cmd[i],
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entry['compile']['cov_opts'],
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en_cov)
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if 'wave_opts' in entry['compile']:
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compile_cmd[i] = process_cmd("<wave_opts>", compile_cmd[i],
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entry['compile']['wave_opts'],
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en_wave)
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sim_cmd = entry['sim']['cmd']
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if 'cov_opts' in entry['sim']:
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sim_cmd = process_cmd("<cov_opts>", sim_cmd,
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entry['sim']['cov_opts'], en_cov)
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if 'wave_opts' in entry['sim']:
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sim_cmd = process_cmd("<wave_opts>", sim_cmd,
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entry['sim']['wave_opts'], en_wave)
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if 'env_var' in entry:
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for env_var in entry['env_var'].split(','):
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for i in range(len(compile_cmd)):
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compile_cmd[i] = re.sub("<"+env_var+">",
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get_env_var(env_var),
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compile_cmd[i])
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sim_cmd = re.sub("<"+env_var+">",
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get_env_var(env_var), sim_cmd)
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return compile_cmd, sim_cmd
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logging.error("Cannot find RTL simulator %0s" % simulator)
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sys.exit(RET_FAIL)
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def rtl_compile(compile_cmd, output_dir, lsf_cmd, opts):
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"""Run the instruction generator
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"""Run the instruction generator
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Args:
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compile_cmd : Compile command
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output_dir : Output directory of the ELF files
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lsf_cmd : LSF command to run compilation
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opts : Compile options for the generator
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"""
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# Compile the TB
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logging.info("Compiling TB")
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for cmd in compile_cmd:
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cmd = re.sub("<out>", output_dir, cmd)
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cmd = re.sub("<cmp_opts>", opts, cmd)
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logging.debug("Compile command: %s" % cmd)
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run_cmd(cmd)
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Args:
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compile_cmd : Compile command
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output_dir : Output directory of the ELF files
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lsf_cmd : LSF command to run compilation
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opts : Compile options for the generator
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"""
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# Compile the TB
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logging.info("Compiling TB")
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for cmd in compile_cmd:
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cmd = re.sub("<out>", output_dir, cmd)
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cmd = re.sub("<cmp_opts>", opts, cmd)
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logging.debug("Compile command: %s" % cmd)
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run_cmd(cmd)
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def rtl_sim(sim_cmd, simulator, test_list, output_dir, bin_dir,
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lsf_cmd, seed, opts):
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"""Run the instruction generator
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"""Run the instruction generator
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Args:
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sim_cmd : Simulation command
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simulator : Simulator being used
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test_list : List of assembly programs
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output_dir : Simulation output directory
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bin_dir : Directory of the ELF files
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lsf_cmd : LSF command to run simulation
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seed : Seed of RTL simulation
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opts : Simulation options
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"""
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check_return_code = True
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# Don't check return code for IUS sims, as a failure will short circuit
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# the entire simulation flow
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if simulator == "ius":
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check_return_code = False
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logging.debug("Disable return code checking for %s simulator" % simulator)
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# Run the RTL simulation
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sim_cmd = re.sub("<out>", output_dir, sim_cmd)
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sim_cmd = re.sub("<sim_opts>", opts, sim_cmd)
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sim_cmd = re.sub("<cwd>", cwd, sim_cmd)
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logging.info("Running RTL simulation...")
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cmd_list = []
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for test in test_list:
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for i in range(test['iterations']):
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rand_seed = get_seed(seed)
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test_sim_cmd = re.sub("<seed>", str(rand_seed), sim_cmd)
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if "sim_opts" in test:
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test_sim_cmd += ' '
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test_sim_cmd += test['sim_opts']
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sim_dir = output_dir + ("/%s.%d" %(test['test'], i))
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run_cmd(("mkdir -p %s" % sim_dir))
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os.chdir(sim_dir)
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binary = ("%s/%s_%d.bin" % (bin_dir, test['test'], i))
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cmd = lsf_cmd + " " + test_sim_cmd + \
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(" +UVM_TESTNAME=%s " % test['rtl_test']) + \
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(" +bin=%s " % binary) + \
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(" -l sim.log ")
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cmd = re.sub('\n', '', cmd)
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if lsf_cmd == "":
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logging.info("Running %s with %s" % (test['rtl_test'], binary))
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run_cmd(cmd, 300, check_return_code = check_return_code)
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else:
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cmd_list.append(cmd)
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if lsf_cmd != "":
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logging.info("Running %0d simulation jobs." % len(cmd_list))
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run_parallel_cmd(cmd_list, 600, check_return_code = check_return_code)
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Args:
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sim_cmd : Simulation command
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simulator : Simulator being used
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test_list : List of assembly programs
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output_dir : Simulation output directory
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bin_dir : Directory of the ELF files
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lsf_cmd : LSF command to run simulation
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seed : Seed of RTL simulation
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opts : Simulation options
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"""
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check_return_code = True
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# Don't check return code for IUS sims, as a failure will short circuit
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# the entire simulation flow
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if simulator == "ius":
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check_return_code = False
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logging.debug("Disable return code checking for %s simulator"
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% simulator)
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# Run the RTL simulation
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sim_cmd = re.sub("<out>", output_dir, sim_cmd)
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sim_cmd = re.sub("<sim_opts>", opts, sim_cmd)
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sim_cmd = re.sub("<cwd>", cwd, sim_cmd)
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logging.info("Running RTL simulation...")
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cmd_list = []
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for test in test_list:
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for i in range(test['iterations']):
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rand_seed = get_seed(seed)
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test_sim_cmd = re.sub("<seed>", str(rand_seed), sim_cmd)
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if "sim_opts" in test:
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test_sim_cmd += ' '
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test_sim_cmd += test['sim_opts']
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sim_dir = output_dir + ("/%s.%d" % (test['test'], i))
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run_cmd(("mkdir -p %s" % sim_dir))
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os.chdir(sim_dir)
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binary = ("%s/%s_%d.bin" % (bin_dir, test['test'], i))
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cmd = (lsf_cmd + " " + test_sim_cmd +
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(" +UVM_TESTNAME=%s " % test['rtl_test']) +
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(" +bin=%s " % binary) +
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(" -l sim.log "))
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cmd = re.sub('\n', '', cmd)
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if lsf_cmd == "":
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logging.info("Running %s with %s" % (test['rtl_test'], binary))
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run_cmd(cmd, 300, check_return_code=check_return_code)
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else:
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cmd_list.append(cmd)
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if lsf_cmd != "":
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logging.info("Running %0d simulation jobs." % len(cmd_list))
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run_parallel_cmd(cmd_list, 600, check_return_code=check_return_code)
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def compare(test_list, iss, output_dir, verbose):
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"""Compare RTL & ISS simulation reult
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"""Compare RTL & ISS simulation reult
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Args:
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test_list : List of assembly programs to be compiled
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iss : List of instruction set simulators
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output_dir : Output directory of the ELF files
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verbose : Verbose logging
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"""
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report = ("%s/regr.log" % output_dir).rstrip()
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for test in test_list:
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compare_opts = test.get('compare_opts', {})
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in_order_mode = compare_opts.get('in_order_mode', 1)
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coalescing_limit = compare_opts.get('coalescing_limit', 0)
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verbose = compare_opts.get('verbose', 0)
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mismatch = compare_opts.get('mismatch_print_limit', 5)
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compare_final = compare_opts.get('compare_final_value_only', 0)
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for i in range(0, test['iterations']):
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elf = ("%s/asm_tests/%s.%d.o" % (output_dir, test['test'], i))
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logging.info("Comparing %s/DUT sim result : %s" % (iss, elf))
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run_cmd(("echo 'Test binary: %s' >> %s" % (elf, report)))
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uvm_log = ("%s/rtl_sim/%s.%d/sim.log" % (output_dir, test['test'], i))
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rtl_log = ("%s/rtl_sim/%s.%d/trace_core_00000000.log" % (output_dir, test['test'], i))
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rtl_csv = ("%s/rtl_sim/%s.%d/trace_core_00000000.csv" % (output_dir, test['test'], i))
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test_name = "%s.%d" % (test['test'], i)
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process_ibex_sim_log(rtl_log, rtl_csv, 1)
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if 'no_post_compare' in test and test['no_post_compare'] == 1:
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check_ibex_uvm_log(uvm_log, "ibex", test_name, report)
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else:
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iss_log = ("%s/instr_gen/%s_sim/%s.%d.log" % (output_dir, iss, test['test'], i))
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iss_csv = ("%s/instr_gen/%s_sim/%s.%d.csv" % (output_dir, iss, test['test'], i))
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if iss == "spike":
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process_spike_sim_log(iss_log, iss_csv)
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elif iss == "ovpsim":
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process_ovpsim_sim_log(iss_log, iss_csv)
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else:
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logging.error("Unsupported ISS" % iss)
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sys.exit(RET_FAIL)
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uvm_result = check_ibex_uvm_log(uvm_log, "ibex", test_name, report, False)
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if not uvm_result:
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check_ibex_uvm_log(uvm_log, "ibex", test_name, report)
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else:
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if 'compare_opts' in test:
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compare_trace_csv(rtl_csv, iss_csv, "ibex", iss, report,
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in_order_mode, coalescing_limit, verbose,
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mismatch, compare_final)
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else:
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compare_trace_csv(rtl_csv, iss_csv, "ibex", iss, report)
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passed_cnt = run_cmd("grep PASSED %s | wc -l" % report).strip()
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failed_cnt = run_cmd("grep FAILED %s | wc -l" % report).strip()
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summary = ("%s PASSED, %s FAILED" % (passed_cnt, failed_cnt))
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logging.info(summary)
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run_cmd(("echo %s >> %s" % (summary, report)))
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logging.info("RTL & ISS regression report is saved to %s" % report)
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Args:
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test_list : List of assembly programs to be compiled
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iss : List of instruction set simulators
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output_dir : Output directory of the ELF files
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verbose : Verbose logging
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"""
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report = ("%s/regr.log" % output_dir).rstrip()
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for test in test_list:
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compare_opts = test.get('compare_opts', {})
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in_order_mode = compare_opts.get('in_order_mode', 1)
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coalescing_limit = compare_opts.get('coalescing_limit', 0)
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verbose = compare_opts.get('verbose', 0)
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mismatch = compare_opts.get('mismatch_print_limit', 5)
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compare_final = compare_opts.get('compare_final_value_only', 0)
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for i in range(0, test['iterations']):
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elf = ("%s/asm_tests/%s.%d.o" % (output_dir, test['test'], i))
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logging.info("Comparing %s/DUT sim result : %s" % (iss, elf))
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run_cmd(("echo 'Test binary: %s' >> %s" % (elf, report)))
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uvm_log = ("%s/rtl_sim/%s.%d/sim.log" %
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(output_dir, test['test'], i))
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rtl_log = ("%s/rtl_sim/%s.%d/trace_core_00000000.log" %
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(output_dir, test['test'], i))
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rtl_csv = ("%s/rtl_sim/%s.%d/trace_core_00000000.csv" %
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(output_dir, test['test'], i))
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test_name = "%s.%d" % (test['test'], i)
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process_ibex_sim_log(rtl_log, rtl_csv, 1)
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if 'no_post_compare' in test and test['no_post_compare'] == 1:
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check_ibex_uvm_log(uvm_log, "ibex", test_name, report)
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else:
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iss_log = ("%s/instr_gen/%s_sim/%s.%d.log" %
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(output_dir, iss, test['test'], i))
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iss_csv = ("%s/instr_gen/%s_sim/%s.%d.csv" %
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(output_dir, iss, test['test'], i))
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if iss == "spike":
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process_spike_sim_log(iss_log, iss_csv)
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elif iss == "ovpsim":
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process_ovpsim_sim_log(iss_log, iss_csv)
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else:
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logging.error("Unsupported ISS" % iss)
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sys.exit(RET_FAIL)
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uvm_result = check_ibex_uvm_log(uvm_log, "ibex",
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test_name, report, False)
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if not uvm_result:
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check_ibex_uvm_log(uvm_log, "ibex", test_name, report)
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else:
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if 'compare_opts' in test:
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compare_trace_csv(rtl_csv, iss_csv, "ibex", iss,
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report, in_order_mode,
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coalescing_limit, verbose,
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mismatch, compare_final)
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else:
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compare_trace_csv(rtl_csv, iss_csv, "ibex",
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iss, report)
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passed_cnt = run_cmd("grep PASSED %s | wc -l" % report).strip()
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failed_cnt = run_cmd("grep FAILED %s | wc -l" % report).strip()
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summary = ("%s PASSED, %s FAILED" % (passed_cnt, failed_cnt))
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logging.info(summary)
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run_cmd(("echo %s >> %s" % (summary, report)))
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logging.info("RTL & ISS regression report is saved to %s" % report)
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# Parse input arguments
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@ -226,7 +244,8 @@ parser.add_argument("--o", type=str, default="./out",
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help="Output directory name")
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parser.add_argument("--riscv_dv_root", type=str, default="",
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help="Root directory of RISCV-DV")
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parser.add_argument("--testlist", type=str, default="riscv_dv_extension/testlist.yaml",
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parser.add_argument("--testlist", type=str,
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default="riscv_dv_extension/testlist.yaml",
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help="Regression testlist")
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parser.add_argument("--test", type=str, default="all",
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help="Test name, 'all' means all tests in the list")
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@ -236,7 +255,8 @@ parser.add_argument("--iterations", type=int, default=0,
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help="Override the iteration count in the test list")
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parser.add_argument("--simulator", type=str, default="vcs",
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help="Simulator used to run the generator, default VCS")
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parser.add_argument("--simulator_yaml", type=str, default="yaml/rtl_simulation.yaml",
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parser.add_argument("--simulator_yaml", type=str,
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default="yaml/rtl_simulation.yaml",
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help="RTL simulator setting YAML")
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parser.add_argument("--iss", type=str, default="spike",
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help="Instruction set simulator")
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@ -253,8 +273,8 @@ parser.add_argument("--en_wave", type=str, default=0,
|
|||
parser.add_argument("--steps", type=str, default="all",
|
||||
help="Run steps: compile,sim,compare")
|
||||
parser.add_argument("--lsf_cmd", type=str, default="",
|
||||
help="LSF command. Run in local sequentially if lsf \
|
||||
command is not specified")
|
||||
help=("LSF command. Run in local sequentially if lsf "
|
||||
"command is not specified"))
|
||||
|
||||
args = parser.parse_args()
|
||||
setup_logging(args.verbose)
|
||||
|
|
@ -267,35 +287,36 @@ bin_dir = ("%s/instr_gen/asm_tests" % args.o)
|
|||
subprocess.run(["mkdir", "-p", output_dir])
|
||||
|
||||
steps = {
|
||||
'compile': args.steps == "all" or re.match("compile", args.steps),
|
||||
'sim': args.steps == "all" or re.match("sim", args.steps),
|
||||
'compare': args.steps == "all" or re.match("compare", args.steps)
|
||||
'compile': args.steps == "all" or re.match("compile", args.steps),
|
||||
'sim': args.steps == "all" or re.match("sim", args.steps),
|
||||
'compare': args.steps == "all" or re.match("compare", args.steps)
|
||||
}
|
||||
|
||||
compile_cmd = []
|
||||
sim_cmd = ""
|
||||
matched_list = []
|
||||
if steps['compile'] or steps['sim']:
|
||||
compile_cmd, sim_cmd = get_simulator_cmd(args.simulator, args.simulator_yaml,
|
||||
args.en_cov, args.en_wave)
|
||||
compile_cmd, sim_cmd = get_simulator_cmd(args.simulator,
|
||||
args.simulator_yaml,
|
||||
args.en_cov, args.en_wave)
|
||||
if steps['sim'] or steps['compare']:
|
||||
process_regression_list(args.testlist, args.test, args.iterations,
|
||||
matched_list, args.riscv_dv_root)
|
||||
if not matched_list:
|
||||
sys.exit("Cannot find %s in %s" % (args.test, args.testlist))
|
||||
process_regression_list(args.testlist, args.test, args.iterations,
|
||||
matched_list, args.riscv_dv_root)
|
||||
if not matched_list:
|
||||
sys.exit("Cannot find %s in %s" % (args.test, args.testlist))
|
||||
|
||||
|
||||
# Compile TB
|
||||
if steps['compile']:
|
||||
rtl_compile(compile_cmd, output_dir, args.lsf_cmd, args.cmp_opts)
|
||||
rtl_compile(compile_cmd, output_dir, args.lsf_cmd, args.cmp_opts)
|
||||
|
||||
|
||||
# Run RTL simulation
|
||||
if steps['sim']:
|
||||
rtl_sim(sim_cmd, args.simulator, matched_list, output_dir, bin_dir,
|
||||
args.lsf_cmd, args.seed, args.sim_opts)
|
||||
rtl_sim(sim_cmd, args.simulator, matched_list, output_dir, bin_dir,
|
||||
args.lsf_cmd, args.seed, args.sim_opts)
|
||||
|
||||
|
||||
# Compare RTL & ISS simulation result.;
|
||||
if steps['compare']:
|
||||
compare(matched_list, args.iss, args.o, args.verbose)
|
||||
compare(matched_list, args.iss, args.o, args.verbose)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue