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Doc: remove draft when mentioning RISC-V Priv Spec v.1.11

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This version of the spec has been ratified in the meantime.
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Pirmin Vogel 2019-06-28 18:52:42 +01:00
parent 2c0aabb6bb
commit ca7bbddd4e
2 changed files with 3 additions and 3 deletions
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2
doc/cs_registers.rst
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@ -3,7 +3,7 @@
Control and Status Registers
============================
Ibex implements all the Control and Status Registers (CSRs) listed in the following table according to the RISC-V Privileged Specification, draft version 1.11.
Ibex implements all the Control and Status Registers (CSRs) listed in the following table according to the RISC-V Privileged Specification, version 1.11.
+---------+--------------------+--------+-----------------------------------------------+
| Address | Name | Access | Description |

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doc/performance_counters.rst
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@ -3,7 +3,7 @@
Performance Counters
====================
Ibex implements performance counters according to the RISC-V Privileged Specification, draft version 1.11 (see Hardware Performance Monitor, Section 3.1.11).
Ibex implements performance counters according to the RISC-V Privileged Specification, version 1.11 (see Hardware Performance Monitor, Section 3.1.11).
The performance counters are placed inside the Control and Status Registers (CSRs) and can be accessed with the ``CSRRW(I)`` and ``CSRRS/C(I)`` instructions.
Ibex implements the clock cycle counter ``mcycle(h)``, the retired instruction counter ``minstret(h)``, as well as the 29 event counters ``mhpmcounter3(h)`` - ``mhpmcounter31(h)`` and the corresponding event selector CSRs ``mhpmevent3`` - ``mhpmevent31``, and the ``mcountinhibit`` CSR to individually enable/disable the counters.
@ -50,7 +50,7 @@ Controlling the counters from software
--------------------------------------
By default, all available counters are enabled after reset.
They can be individually enabled/disabled by overwriting the corresponding bit in the ``mcountinhibit`` CSR at address ``0x320`` as described in the RISC-V Privileged Specification, draft version 1.11 (see Machine Counter-Inhibit CSR, Section 3.1.13).
They can be individually enabled/disabled by overwriting the corresponding bit in the ``mcountinhibit`` CSR at address ``0x320`` as described in the RISC-V Privileged Specification, version 1.11 (see Machine Counter-Inhibit CSR, Section 3.1.13).
In particular, to enable/disable ``mcycle(h)``, bit 0 must be written. For ``minstret(h)``, it is bit 2. For event counter ``mhpmcounterX(h)``, it is bit X.
The lower 32 bits of all counters can be accessed through the base register, whereas the upper 32 bits are accessed through the ``h``-register.