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Remove csr_restore_dret_i signal

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This signal was used to restore `mstatus` when executing DRET.
But this is not needed as `mstatus` is not modified when entering
debug mode.
This commit is contained in:
Pirmin Vogel 2019-07-17 18:24:59 +01:00 • committed by Philipp Wagner
parent 964e62afee
commit cee2e9396f
4 changed files with 3 additions and 17 deletions
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3
rtl/ibex_controller.sv
View file

@ -86,7 +86,6 @@ module ibex_controller (
output logic csr_save_if_o,
output logic csr_save_id_o,
output logic csr_restore_mret_id_o,
output logic csr_restore_dret_id_o,
output logic csr_save_cause_o,
output logic [31:0] csr_mtval_o,
@ -203,7 +202,6 @@ module ibex_controller (
csr_save_if_o = 1'b0;
csr_save_id_o = 1'b0;
csr_restore_mret_id_o = 1'b0;
csr_restore_dret_id_o = 1'b0;
csr_save_cause_o = 1'b0;
csr_mtval_o = '0;
@ -519,7 +517,6 @@ module ibex_controller (
end else if (dret_insn_i) begin
pc_mux_o = PC_DRET;
pc_set_o = 1'b1;
csr_restore_dret_id_o = 1'b1;
debug_mode_d = 1'b0;
end else if (wfi_insn_i) begin
ctrl_fsm_ns = WAIT_SLEEP;

9
rtl/ibex_core.sv
View file

@ -199,7 +199,6 @@ module ibex_core #(
logic csr_save_if;
logic csr_save_id;
logic csr_restore_mret_id;
logic csr_restore_dret_id;
logic csr_save_cause;
logic [31:0] csr_mtvec;
logic [31:0] csr_mtval;
@ -403,10 +402,9 @@ module ibex_core #(
// CSR ID/EX
.csr_access_o ( csr_access ),
.csr_op_o ( csr_op ),
.csr_save_if_o ( csr_save_if ), // control signal to save pc
.csr_save_id_o ( csr_save_id ), // control signal to save pc
.csr_restore_mret_id_o ( csr_restore_mret_id ), // control signal to restore pc
.csr_restore_dret_id_o ( csr_restore_dret_id ), // control signal to restore pc
.csr_save_if_o ( csr_save_if ), // control signal to save PC
.csr_save_id_o ( csr_save_id ), // control signal to save PC
.csr_restore_mret_id_o ( csr_restore_mret_id ), // restore mstatus upon MRET
.csr_save_cause_o ( csr_save_cause ),
.csr_mtval_o ( csr_mtval ),
.illegal_csr_insn_i ( illegal_csr_insn_id ),
@ -596,7 +594,6 @@ module ibex_core #(
.csr_save_if_i ( csr_save_if ),
.csr_save_id_i ( csr_save_id ),
.csr_restore_mret_i ( csr_restore_mret_id ),
.csr_restore_dret_i ( csr_restore_dret_id ),
.csr_save_cause_i ( csr_save_cause ),
.csr_mtvec_i ( csr_mtvec ),
.csr_mcause_i ( exc_cause ),

6
rtl/ibex_cs_registers.sv
View file

@ -72,7 +72,6 @@ module ibex_cs_registers #(
input logic csr_save_if_i,
input logic csr_save_id_i,
input logic csr_restore_mret_i,
input logic csr_restore_dret_i,
input logic csr_save_cause_i,
input logic [31:0] csr_mtvec_i,
input ibex_pkg::exc_cause_e csr_mcause_i,
@ -489,11 +488,6 @@ module ibex_cs_registers #(
mcause_d = mstack_cause_q;
end // csr_restore_mret_i
csr_restore_dret_i: begin // DRET
mstatus_d.mie = mstatus_q.mpie;
mstatus_d.mpie = 1'b1;
end // csr_restore_dret_i
default:;
endcase
end

2
rtl/ibex_id_stage.sv
View file

@ -90,7 +90,6 @@ module ibex_id_stage #(
output logic csr_save_if_o,
output logic csr_save_id_o,
output logic csr_restore_mret_id_o,
output logic csr_restore_dret_id_o,
output logic csr_save_cause_o,
output logic [31:0] csr_mtval_o,
input logic illegal_csr_insn_i,
@ -453,7 +452,6 @@ module ibex_id_stage #(
.csr_save_if_o ( csr_save_if_o ),
.csr_save_id_o ( csr_save_id_o ),
.csr_restore_mret_id_o ( csr_restore_mret_id_o ),
.csr_restore_dret_id_o ( csr_restore_dret_id_o ),
.csr_save_cause_o ( csr_save_cause_o ),
.csr_mtval_o ( csr_mtval_o ),