Fix some synthesis warnings

alu.sv

@@ -90,6 +90,7 @@ module riscv_alu
   //                                                                                      //
   //////////////////////////////////////////////////////////////////////////////////////////
 
+  logic        adder_op_b_negate;
   logic [31:0] adder_op_a, adder_op_b;
   logic [35:0] adder_in_a, adder_in_b;
   logic [31:0] adder_result;
@@ -185,6 +186,9 @@ module riscv_alu
   ////////////////////////////////////////
 
   logic        shift_left;         // should we shift left
+  logic        shift_use_round;
+  logic        shift_arithmetic;
+
   logic [31:0] shift_amt_left;     // amount of shift, if to the left
   logic [31:0] shift_amt;          // amount of shift, to the right
   logic [31:0] shift_amt_int;      // amount of shift, used for the actual shifters

exc_controller.sv

@@ -109,7 +109,7 @@ module riscv_exc_controller
       begin
         if (irq_i[i]) begin
           cause_int[5]   = 1'b1;
-          cause_int[4:0] = i;
+          cause_int[4:0] = $unsigned(i);
         end
       end
     end

if_stage.sv

@@ -128,11 +128,7 @@ module riscv_if_stage
       `EXC_PC_IRQ:     exc_pc = { boot_addr_i[31:8], 1'b0, exc_vec_pc_mux_i[4:0], 2'b0 };
       // TODO: Add case for EXC_PC_STORE as soon as it differs from load
 
-      default: begin
-        // synopsys translate_off
-        $display("%t: Illegal exc pc_mux value (%0d)!", $time, exc_pc_mux_i);
-        // synopsys translate_on
-      end
+      default:;
     endcase
   end
 
@@ -149,11 +145,7 @@ module riscv_if_stage
       `PC_ERET:      fetch_addr_n = exception_pc_reg_i; // PC is restored when returning from IRQ/exception
       `PC_DBG_NPC:   fetch_addr_n = dbg_npc_i;          // PC is taken from debug unit
 
-      default: begin
-        // synopsys translate_off
-        $display("%t: Illegal pc_mux_sel value (%0d)!", $time, pc_mux_i);
-        // synopsys translate_on
-      end
+      default:;
     endcase
   end