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Fix rst syntax

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Signed-off-by: Michael Gielda <mgielda@antmicro.com>
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Michael Gielda 2020-04-17 19:13:49 +02:00 • committed by Rupert Swarbrick
parent 2be109ecca
commit d6d23917ae
1 changed files with 14 additions and 14 deletions
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6
doc/verification.rst
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@ -85,10 +85,10 @@ Prerequisites & Environment Setup
In order to run the co-simulation flow, you'll need:
- A SystemVerilog simulator that supports UVM. The flow is currently
- A SystemVerilog simulator that supports UVM. The flow is currently
tested with VCS.
- A RISC-V instruction set simulator. For example, Spike_ or
- A RISC-V instruction set simulator. For example, Spike_ or
OVPsim_. Note that Spike must be configured with
``--enable-commitlog`` and ``--enable-misaligned``. The commit log
is needed to track the instructions that were executed and
@ -96,7 +96,7 @@ In order to run the co-simulation flow, you'll need:
handles misaligned accesses in hardware (rather than jumping to a
trap handler).
- A working RISC-V toolchain (to compile / assemble the generated
- A working RISC-V toolchain (to compile / assemble the generated
programs before simulating them). Either download and build the
`RISC-V GNU compiler toolchain <riscv-toolchain-source_>`_ or
(quicker) download a `pre-built toolchain