[rtl] Hard wire dcsr.stepie to 0

This indicates interrupts do not occur in single step mode.

Fixes #1279

rtl/ibex_controller.sv

@@ -316,9 +316,10 @@ module ibex_controller #(
   // memory) before it has had anything to single step.
   // Also enter debug mode on a trigger match (hardware breakpoint)
 
-  // Set `do_single_step_q` when a valid instruction is seen outside of debug mode. The first valid
-  // instruction on debug mode entry will clear it. Hold its value when there is no valid
-  // instruction so `do_single_step_d` remains asserted until debug mode is entered.
+  // Set `do_single_step_q` when a valid instruction is seen outside of debug mode and core is in
+  // single step mode. The first valid instruction on debug mode entry will clear it. Hold its value
+  // when there is no valid instruction so `do_single_step_d` remains asserted until debug mode is
+  // entered.
   assign do_single_step_d = instr_valid_i ? ~debug_mode_q & debug_single_step_i : do_single_step_q;
   // Enter debug mode due to:
   // * external `debug_req_i`

rtl/ibex_cs_registers.sv

@@ -564,6 +564,9 @@ module ibex_cs_registers #(
           // Read-only for SW
           dcsr_d.cause = dcsr_q.cause;
 
+          // Interrupts always disabled during single stepping
+          dcsr_d.stepie = 1'b0;
+
           // currently not supported:
           dcsr_d.nmip = 1'b0;
           dcsr_d.mprven = 1'b0;