[dv] Remove riscv_perf_counter_test

This test doesn't actually check the performance counters, it just runs
a random instruction test and dumps the performance counters at the end
for some final checking. That checking does not exist. The test is
currently broken as well so just remove it as it adds nothing to the
regression.

dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml

@@ -553,19 +553,6 @@
   compare_opts:
     compare_final_value_only: 1
 
-- test: riscv_perf_counter_test
-  description: >
-    Dump performance counters at EOT for any analysis
-  iterations: 5
-  gen_test: riscv_rand_instr_test
-  gen_opts: >
-    +require_signature_addr=1
-    +instr_cnt=10000
-    +num_of_sub_program=5
-  rtl_test: core_ibex_perf_test
-  sim_opts: >
-    +require_signature_addr=1
-
 - test: riscv_debug_single_step_test
   description: >
     Randomly assert debug_req_i, and set dcsr.step to make ibex execute one insn then re-enter debug mode