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[dv,test] Enable FENCE.I instruction generation

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Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
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Canberk Topal 2022-07-21 23:31:39 +01:00 • committed by Canberk Topal
parent ec7706cc9f
commit d84cd116c2
1 changed files with 1 additions and 1 deletions
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dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv
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@ -46,7 +46,7 @@ privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE, USER_MODE};
// Unsupported instructions
// Avoid generating these instructions in regular regression
// FENCE.I is intentionally treated as illegal instruction by ibex core
riscv_instr_name_t unsupported_instr[] = {FENCE_I};
riscv_instr_name_t unsupported_instr[] = {};
// Specify whether processor supports unaligned loads and stores
bit support_unaligned_load_store = 1'b1;