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[dv] Add coverage for debug requests and interrupts while executing a dummy instruction

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Signed-off-by: Andreas Kurth <adk@lowrisc.org>
This commit is contained in:
Andreas Kurth 2022-11-04 16:33:41 +00:00 • committed by Canberk Topal
parent 550c9b2903
commit dd0063e394
2 changed files with 17 additions and 0 deletions
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4
doc/03_reference/coverage_plan.rst
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@ -382,3 +382,7 @@ There must be a documented reason a particular bin is added to the illegal or ig
* ``dummy_instr_config_cross`` - Dummy Instruction Type x Dummy Instruction Insertion Frequency to explore all possible configurations.
* ``rf_ecc_err_cross`` - ECC Error on Port A x ECC Error on Port B to explore all possible combinations of reported ECC errors.
* ``debug_req_dummy_instr_{if,id,wb}_stage_cross`` - The IF, ID/EX, or WB stage handles a dummy instruction while a debug request arrives.
* ``irq_pending_dummy_instr_{if,id,wb}_stage_cross`` - The IF, ID/EX, or WB stage handles a dummy instruction while an IRQ is pending.

13
dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
View file

@ -711,11 +711,24 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
ignore_bins ignore = !binsof(cp_csr_write) intersect {`DEBUG_CSRS};
}
// V2S Crosses
dummy_instr_config_cross: cross cp_dummy_instr_type, cp_dummy_instr_mask
iff (cs_registers_i.dummy_instr_en_o);
rf_ecc_err_cross: cross cp_rf_a_ecc_err, cp_rf_b_ecc_err
iff (id_stage_i.instr_valid_i);
// Each stage sees a debug request while executing a dummy instruction.
debug_req_dummy_instr_if_stage_cross: cross cp_debug_req, cp_dummy_instr_if_stage;
debug_req_dummy_instr_id_stage_cross: cross cp_debug_req, cp_dummy_instr_id_stage;
debug_req_dummy_instr_wb_stage_cross: cross cp_debug_req, cp_dummy_instr_wb_stage;
// Each stage sees an interrupt request while executing a dummy instruction.
irq_pending_dummy_instr_if_stage_cross: cross cp_irq_pending, cp_dummy_instr_if_stage;
irq_pending_dummy_instr_id_stage_cross: cross cp_irq_pending, cp_dummy_instr_id_stage;
irq_pending_dummy_instr_wb_stage_cross: cross cp_irq_pending, cp_dummy_instr_wb_stage;
endgroup
bit en_uarch_cov;