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Avoid two combinatorial loop warnings in riscv_compliance suite

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We do this by pulling the definition of host_addr_o and host_req_o out
of an always_comb process in riscv_testutil.sv.

When set inside the process, Verilator warns about a combinatorial
loop. This happens because a read request could go out on the bus and
appear again (combinatorially) on the slave interface, setting
read_signature_and_terminate. This doesn't actually happen (because
read_signature_and_terminate only takes effect when we are in state
WAIT), but Verilator's sensitivity tracking isn't fine-grained enough
to notice.
This commit is contained in:
Rupert Swarbrick 2020-03-02 13:28:47 +00:00 • committed by Rupert Swarbrick
parent 210634586d
commit ddb34bcb75
1 changed files with 5 additions and 4 deletions
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9
dv/riscv_compliance/rtl/riscv_testutil.sv
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@ -106,8 +106,6 @@ module riscv_testutil (
logic [31:0] read_addr_d, read_addr_q;
always_comb begin
state_d = state_q;
host_req_o = 1'b0;
unique case (state_q)
WAIT: begin
if (read_signature_and_terminate) begin
@ -119,8 +117,6 @@ module riscv_testutil (
end
READ: begin
host_req_o = 1'b1;
host_addr_o = read_addr_q;
if (host_gnt_i) begin
read_addr_d = read_addr_q + 4;
if (read_addr_d == end_signature_addr_q) begin
@ -142,6 +138,11 @@ module riscv_testutil (
endcase
end
// These are the address and read request bits, respectively of the
// TestUtilHost master port.
assign host_addr_o = read_addr_q;
assign host_req_o = (state_q == READ);
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
state_q <= WAIT;