ibex_core: Use correct width for param assignments

These parameters are of type bit, we need to assign a value of the
correct width to avoid Verilator lint warnings.

rtl/ibex_core.sv

@@ -11,13 +11,13 @@
  * Top level module of the ibex RISC-V core
  */
 module ibex_core #(
-    parameter bit          PMPEnable        = 0,
+    parameter bit          PMPEnable        = 1'b0,
     parameter int unsigned PMPGranularity   = 0,
     parameter int unsigned PMPNumRegions    = 4,
     parameter int unsigned MHPMCounterNum   = 0,
     parameter int unsigned MHPMCounterWidth = 40,
-    parameter bit RV32E                     = 0,
-    parameter bit RV32M                     = 1,
+    parameter bit          RV32E            = 1'b0,
+    parameter bit          RV32M            = 1'b1,
     parameter int unsigned DmHaltAddr       = 32'h1A110800,
     parameter int unsigned DmExceptionAddr  = 32'h1A110808
 ) (

rtl/ibex_core_tracing.sv

@@ -9,8 +9,8 @@
 module ibex_core_tracing #(
     parameter int unsigned MHPMCounterNum   = 8,
     parameter int unsigned MHPMCounterWidth = 40,
-    parameter bit RV32E                     = 0,
-    parameter bit RV32M                     = 1,
+    parameter bit RV32E                     = 1'b0,
+    parameter bit RV32M                     = 1'b1,
     parameter int unsigned DmHaltAddr       = 32'h1A110800,
     parameter int unsigned DmExceptionAddr  = 32'h1A110808
 ) (