Update riscv-isa-sim to lowrisc/riscv-isa-sim@a4b823a1

Update code from upstream repository https://github.com/lowrisc/riscv-
isa-sim to revision a4b823a1c7a260b532e1aa41b4d929e9634a7222

* Remove personal paths from Makefile (Marno van der Maas)
* Remove trailing whitespace (Marno van der Maas)

Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>

vendor/riscv-isa-sim/tests/mseccfg/Makefile

@@ -2,8 +2,8 @@
 
 XLEN ?= 32
 VLEN ?= 1024
-RISCV_TOOL ?= /home/saad/Downloads/lowrisc-toolchain-gcc-rv32imcb-20220524-1/bin/
-SPIKE_PATH ?= /home/saad/work/riscv-isa-sim/build
+RISCV_TOOL ?= ~/lowrisc-toolchain-gcc-rv32imcb-20220524-1/bin/
+SPIKE_PATH ?= ~/riscv-isa-sim/build
 SAIL_EMULATOR_PATH = /home/scratch.soberl_maxwell/arch1/sail_2021/sail-riscv/c_emulator
 
 SSP_OPT ?=
@@ -13,7 +13,7 @@ LIB_PATH = .
 # ../ctests/nvrvv_lib.c
 COMMON_FILES = \
 	$(LIB_PATH)/crt.S \
-	$(LIB_PATH)/syscalls.c 
+	$(LIB_PATH)/syscalls.c
 
 TEST_PATH = ./gengen_src/outputs
 
@@ -26,7 +26,7 @@ CFLAGS = -march=rv$(XLEN)imafd -O2 -I . -I ./$(LIB_PATH) -I ../softfloat -I ../r
 	-fno-builtin-printf -fdata-sections -fno-section-anchors $(SSP_OPT) -DPRINTF_SUPPORTED=1
 LDFLAGS = -mcmodel=medany -static -nostdlib -nostartfiles -lm -lgcc \
 	-T $(LIB_PATH)/mseccfg_test.ld  -Wl,-M -Wl,-Map=link.log
-	
+
 # must enable 'C', maybe used in pk
 # 8M for TCM memories
 # 16M for L2 memories
@@ -36,10 +36,10 @@ default:
 	@echo "make gen, to generate all test cases with gengen"
 	@echo "make run, to run all test cases"
 	@echo "set OBJECTS variant to select specified test case"
-	
+
 gen:
 	cd gengen_src; $(MAKE); $(MAKE) gen;
-	
+
 $(OBJECTS):
 	@$(RISCV_TOOL)/riscv$(XLEN)-unknown-elf-gcc $(CFLAGS) $(TEST_PATH)/$@.c $(COMMON_FILES) $(LDFLAGS) -o a.out 
 	@echo Running $(TEST_PATH)/$@.c - command - $(RISCV_TOOL)/riscv$(XLEN)-unknown-elf-gcc $(CFLAGS) $(TEST_PATH)/$@.c $(COMMON_FILES) $(LDFLAGS) -o a.out
@@ -53,18 +53,18 @@ ifeq ($(PERF), 0)
 #	sed -i '0,/ nop/d' $@_pc.log
 #	sed -i '/ nop/q' $@_pc.log
 endif
-	
+
 run: $(OBJECTS)
 
 clean:
 	rm *.s *.o *.i *.ss *.out *.log *.bin
-	
+
 log:
 	$(SPIKE_PATH)/spike $(SIM_ISA) -m0x100000:0x200000 -l a.out > 1.log 2>&1
 	$(SAIL_EMULATOR_PATH)/riscv_sim_RV64 --enable-pmp a.out > 2.log 2>&1
-	
+
 env:
 	echo $(ALL_TEST)
-	
+
 
 .PHONY: gen $(OBJECTS) clean

vendor/riscv_isa_sim.lock.hjson

@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/lowrisc/riscv-isa-sim
-    rev: a7c5d5d830e4095aa86580579efc46335fbc2f80
+    rev: a4b823a1c7a260b532e1aa41b4d929e9634a7222
   }
 }