[syn] Use sv2v for prim_generic_buf

Convert `prim_generic_buf` to Verilog as well.
Also, replace 'prim_buf' with 'prim_generic_buf' whenever we see a
`prim_buf` in a generated Verilog file.

Fixes #1557

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This commit is contained in:
Canberk Topal 2022-05-31 16:32:18 +01:00 committed by Canberk Topal
parent e1f614887e
commit ea4e9383db

View file

@ -32,10 +32,26 @@ source syn_setup.sh
# use sv2v to convert all SystemVerilog files to Verilog
#-------------------------------------------------------------------------
LR_DEP_SOURCES=(
"../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv"
)
mkdir -p "$LR_SYNTH_OUT_DIR/generated"
mkdir -p "$LR_SYNTH_OUT_DIR/log"
mkdir -p "$LR_SYNTH_OUT_DIR/reports/timing"
# Convert dependency sources
for file in ${LR_DEP_SOURCES[@]}; do
module=`basename -s .sv $file`
sv2v \
--define=SYNTHESIS --define=YOSYS \
-I../vendor/lowrisc_ip/ip/prim/rtl \
$file \
> $LR_SYNTH_OUT_DIR/generated/${module}.v
done
# Convert core sources
for file in ../rtl/*.sv; do
module=`basename -s .sv $file`
@ -45,7 +61,7 @@ for file in ../rtl/*.sv; do
fi
sv2v \
--define=SYNTHESIS \
--define=SYNTHESIS --define=YOSYS \
../rtl/*_pkg.sv \
../vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv \
../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv \
@ -53,6 +69,10 @@ for file in ../rtl/*.sv; do
-I../vendor/lowrisc_ip/dv/sv/dv_utils \
$file \
> $LR_SYNTH_OUT_DIR/generated/${module}.v
# Make sure auto-generated primitives are resolved to generic primitives
# where available.
sed -i 's/prim_buf/prim_generic_buf/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
done
# remove tracer (not needed for synthesis)