github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-20 11:57:12 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

[dv] Write ePMP tests and enable ePMP in DV

Browse source 
- Enable epmp in riscv_core_settings.sv
- Bump CI and Spike version in `ci/vars.yml`
- Enable full random PMP test
- Create tests for machine mode lockdown (MML)
  - Code execute only, rest read/write
  - All regions execute only
  - All regions read only
- Create test for machine mode whitelist policy (MMWP)
- Create test for rule lock bypass (RLB)

Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
This commit is contained in:
Marno van der Maas 2022-07-07 17:24:59 +01:00 • committed by Marno van der Maas
parent b98efe7cbe
commit ef86c30341
3 changed files with 175 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

4
ci/vars.yml
View file

@ -7,10 +7,10 @@
# end up as float otherwise).
variables:
VERILATOR_VERSION: "4.104"
IBEX_COSIM_VERSION: "0.2"
IBEX_COSIM_VERSION: "0.3"
RISCV_TOOLCHAIN_TAR_VERSION: "20220210-1"
RISCV_TOOLCHAIN_TAR_VARIANT: "lowrisc-toolchain-gcc-rv32imcb"
RISCV_COMPLIANCE_GIT_VERSION: "844c6660ef3f0d9b96957991109dfd80cc4938e2"
VERIBLE_VERSION: "v0.0-2135-gb534c1fe"
# lowRISC-internal version numbers of Ibex-specific Spike builds.
SPIKE_IBEX_VERSION: "20220308-git-20a886cba76dd80a23b548743ab3c73b19f65e41"
SPIKE_IBEX_VERSION: "20220516-git-9af9730baf7b956c3072c1b436d867aca5ef8f4c"

2
dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv
View file

@ -66,7 +66,7 @@ int max_interrupt_vector_num = 32;
bit support_pmp = 1;
// Enhanced physical memory protection support
bit support_epmp = 0;
bit support_epmp = 1;
// Debug mode support
bit support_debug_mode = 1;

190
dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
View file

@ -678,6 +678,7 @@
+set_mstatus_mprv=1
+pmp_max_offset=00024000
+enable_write_pmp_csr=1
+mseccfg=MML:0,MMWP:0,RLB:0
rtl_test: core_ibex_base_test
rtl_params:
PMPEnable: 1
@ -710,6 +711,7 @@
+pmp_region_14=X:0,W:0,R:0
+pmp_region_15=X:0,W:0,R:0
+enable_write_pmp_csr=1
+mseccfg=MML:0,MMWP:0,RLB:0
rtl_test: core_ibex_base_test
rtl_params:
PMPEnable: 1
@ -727,28 +729,180 @@
+pmp_max_offset=00024000
+enable_write_pmp_csr=1
+directed_instr_0=riscv_load_store_rand_addr_instr_stream,50
+mseccfg=MML:0,MMWP:0,RLB:0
rtl_test: core_ibex_base_test
rtl_params:
PMPEnable: 1
# TODO(udinator) this test is failing with arbitrary timeouts, need to fix this.
#- test: riscv_pmp_full_random_test
# desc: >
# Completely randomize the boot mode, mstatus.mprv, and all PMP configuration,
# and allow PMP regions to overlap.
# A large number of iterations will be required since this introduces a huge
# state space of configurations.
# iterations: 100
# gen_test: riscv_rand_instr_test
# gen_opts: >
# +instr_cnt=6000
# +pmp_max_offset=00024000
# +pmp_randomize=1
# +pmp_allow_addr_overlap=1
# +enable_write_pmp_csr=1
# rtl_test: core_ibex_base_test
# rtl_params:
# PMPEnable: 1
- test: riscv_pmp_full_random_test
desc: >
Completely randomize the boot mode, mstatus.mprv, and all PMP configuration,
and allow PMP regions to overlap.
A large number of iterations will be required since this introduces a huge
state space of configurations.
iterations: 100
gen_test: riscv_rand_instr_test
gen_opts: >
+instr_cnt=6000
+pmp_max_offset=00024000
+set_mstatus_mprv=1
+pmp_randomize=1
+pmp_allow_addr_overlap=1
+enable_write_pmp_csr=1
rtl_test: core_ibex_base_test
rtl_params:
PMPEnable: 1
- test: riscv_epmp_mml_test
desc: >
An enhanced PMP machine mode lockdown test - initialization and main
regions are set to execute only in both M and U modes. All other regions
are set to read/write only. Exceptions when reading/writing code or
executing data. Randomize mstatus.mprv.
iterations: 3
gen_test: riscv_rand_instr_test
gen_opts: >
+instr_cnt=6000
+set_mstatus_mprv=1
+pmp_max_offset=00024000
+pmp_region_0=L:1,X:0,W:1,R:0
+pmp_region_1=L:1,X:0,W:1,R:0
+pmp_region_2=L:0,X:1,W:1,R:0
+pmp_region_3=L:0,X:1,W:1,R:0
+pmp_region_4=L:0,X:1,W:1,R:0
+pmp_region_5=L:0,X:1,W:1,R:0
+pmp_region_6=L:0,X:1,W:1,R:0
+pmp_region_7=L:0,X:1,W:1,R:0
+pmp_region_8=L:0,X:1,W:1,R:0
+pmp_region_9=L:0,X:1,W:1,R:0
+pmp_region_10=L:0,X:1,W:1,R:0
+pmp_region_11=L:0,X:1,W:1,R:0
+pmp_region_12=L:0,X:1,W:1,R:0
+pmp_region_13=L:0,X:1,W:1,R:0
+pmp_region_14=L:0,X:1,W:1,R:0
+pmp_region_15=L:0,X:1,W:1,R:0
+enable_write_pmp_csr=1
+mseccfg=MML:1,MMWP:0,RLB:0
rtl_test: core_ibex_base_test
rtl_params:
PMPEnable: 1
- test: riscv_epmp_mml_execute_only_test
desc: >
An enhanced PMP machine mode lockdown test - all PMP regions are set to
execute only. Exception is expected on any store or load. Randomize
mstatus.mprv.
iterations: 3
gen_test: riscv_rand_instr_test
gen_opts: >
+instr_cnt=6000
+set_mstatus_mprv=1
+pmp_max_offset=00024000
+pmp_region_0=L:1,X:0,W:1,R:0
+pmp_region_1=L:1,X:0,W:1,R:0
+pmp_region_2=L:1,X:0,W:1,R:0
+pmp_region_3=L:1,X:0,W:1,R:0
+pmp_region_4=L:1,X:0,W:1,R:0
+pmp_region_5=L:1,X:0,W:1,R:0
+pmp_region_6=L:1,X:0,W:1,R:0
+pmp_region_7=L:1,X:0,W:1,R:0
+pmp_region_8=L:1,X:0,W:1,R:0
+pmp_region_9=L:1,X:0,W:1,R:0
+pmp_region_10=L:1,X:0,W:1,R:0
+pmp_region_11=L:1,X:0,W:1,R:0
+pmp_region_12=L:1,X:0,W:1,R:0
+pmp_region_13=L:1,X:0,W:1,R:0
+pmp_region_14=L:1,X:0,W:1,R:0
+pmp_region_15=L:1,X:0,W:1,R:0
+enable_write_pmp_csr=1
+mseccfg=MML:1,MMWP:0,RLB:0
rtl_test: core_ibex_base_test
rtl_params:
PMPEnable: 1
- test: riscv_epmp_mml_read_only_test
desc: >
An enhanced PMP machine mode lockdown test - all PMP regions are set to
shared read only. Exception is expected right after enabling MML. Randomize
mstatus.mprv.
iterations: 3
gen_test: riscv_rand_instr_test
gen_opts: >
+instr_cnt=6000
+set_mstatus_mprv=1
+pmp_max_offset=00024000
+pmp_region_0=L:1,X:1,W:1,R:1
+pmp_region_1=L:1,X:1,W:1,R:1
+pmp_region_2=L:1,X:1,W:1,R:1
+pmp_region_3=L:1,X:1,W:1,R:1
+pmp_region_4=L:1,X:1,W:1,R:1
+pmp_region_5=L:1,X:1,W:1,R:1
+pmp_region_6=L:1,X:1,W:1,R:1
+pmp_region_7=L:1,X:1,W:1,R:1
+pmp_region_8=L:1,X:1,W:1,R:1
+pmp_region_9=L:1,X:1,W:1,R:1
+pmp_region_10=L:1,X:1,W:1,R:1
+pmp_region_11=L:1,X:1,W:1,R:1
+pmp_region_12=L:1,X:1,W:1,R:1
+pmp_region_13=L:1,X:1,W:1,R:1
+pmp_region_14=L:1,X:1,W:1,R:1
+pmp_region_15=L:1,X:1,W:1,R:1
+enable_write_pmp_csr=1
+mseccfg=MML:1,MMWP:0,RLB:0
rtl_test: core_ibex_base_test
rtl_params:
PMPEnable: 1
- test: riscv_epmp_mmwp_test
desc: >
An enhanced PMP machine mode whitelist policy - all PMP regions will be
configured to default setting, enabling all forms of accesses, expect that
an exception when machine mode access memory not in PMP. Randomize
mstatus.mprv.
iterations: 3
gen_test: riscv_rand_instr_test
gen_opts: >
+instr_cnt=6000
+set_mstatus_mprv=1
+pmp_max_offset=00024000
+enable_write_pmp_csr=1
+mseccfg=MML:0,MMWP:1,RLB:0
rtl_test: core_ibex_base_test
rtl_params:
PMPEnable: 1
- test: riscv_epmp_rlb_test
desc: >
An enhanced PMP rule lock bypass - all PMP regions are locked and enable
all forms of accesses, expect that no exception will be thrown even when
trying to change locked entries. Randomize mstatus.mprv.
iterations: 3
gen_test: riscv_rand_instr_test
gen_opts: >
+instr_cnt=6000
+set_mstatus_mprv=1
+pmp_max_offset=00024000
+pmp_region_0=L:1,X:1,W:1,R:1
+pmp_region_1=L:1,X:1,W:1,R:1
+pmp_region_2=L:1,X:1,W:1,R:1
+pmp_region_3=L:1,X:1,W:1,R:1
+pmp_region_4=L:1,X:1,W:1,R:1
+pmp_region_5=L:1,X:1,W:1,R:1
+pmp_region_6=L:1,X:1,W:1,R:1
+pmp_region_7=L:1,X:1,W:1,R:1
+pmp_region_8=L:1,X:1,W:1,R:1
+pmp_region_9=L:1,X:1,W:1,R:1
+pmp_region_10=L:1,X:1,W:1,R:1
+pmp_region_11=L:1,X:1,W:1,R:1
+pmp_region_12=L:1,X:1,W:1,R:1
+pmp_region_13=L:1,X:1,W:1,R:1
+pmp_region_14=L:1,X:1,W:1,R:1
+pmp_region_15=L:1,X:1,W:1,R:1
+enable_write_pmp_csr=1
+mseccfg=MML:0,MMWP:0,RLB:1
rtl_test: core_ibex_base_test
rtl_params:
PMPEnable: 1
# Disable cosim for bitmanip tests for now as Ibex implements a different
# version of the spec compared to the Spike version used for the cosim.