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Update documentation on CSRs and performance counters
This commit is contained in:
Pirmin Vogel
parent
d5a89b571f
commit
effa61c684
5 changed files with 219 additions and 227 deletions
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@ -3,35 +3,62 @@
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Control and Status Registers
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============================
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Ibex does not implement all control and status registers specified in the RISC-V privileged specifications, but is limited to the registers that were needed for the PULP system. The reason for this is that we wanted to keep the footprint of the core as low as possible and avoid any overhead that we do not explicitly need.
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Ibex implements all the Control and Status Registers (CSRs) listed in the following table according to the RISC-V Privileged Specification, draft version 1.11.
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.. tabularcolumns:: |p{1cm}|p{.6cm}|p{.6cm}|p{1cm}|p{1cm}|p{1.5cm}|p{1.2cm}|p{6cm}|
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+----------------------------+--------+---------+--------+-----------------------------------+
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| CSR Address | Hex | Name | Access | Description |
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+-------+-----+-----+--------+--------+---------+--------+-----------------------------------+
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| 11:10 | 9:8 | 7:6 | 5:0 | | | | |
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+=======+=====+=====+========+========+=========+========+===================================+
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| 00 | 11 | 00 | 000000 | 0x300 | MSTATUS | R/W | Machine Status |
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+-------+-----+-----+--------+--------+---------+--------+-----------------------------------+
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| 00 | 11 | 00 | 000101 | 0x305 | MTVEC | R | Machine Trap-Vector Base Address |
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+-------+-----+-----+--------+--------+---------+--------+-----------------------------------+
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| 00 | 11 | 01 | 000001 | 0x341 | MEPC | R/W | Machine Exception Program Counter |
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+-------+-----+-----+--------+--------+---------+--------+-----------------------------------+
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| 00 | 11 | 01 | 000010 | 0x342 | MCAUSE | R/W | Machine Trap Cause |
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+-------+-----+-----+--------+--------+---------+--------+-----------------------------------+
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| 01 | 11 | 00 | 0xxxxx | 0x780- | PCCRs | R/W | Performance Counter Counter |
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| | | | | 0x79F | | | Registers |
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+-------+-----+-----+--------+--------+---------+--------+-----------------------------------+
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| 01 | 11 | 10 | 100000 | 0x7A0 | PCER | R/W | Performance Counter Enable |
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+-------+-----+-----+--------+--------+---------+--------+-----------------------------------+
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| 01 | 11 | 10 | 100001 | 0x7A1 | PCMR | R/W | Performance Counter Mode |
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+-------+-----+-----+--------+--------+---------+--------+-----------------------------------+
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| 11 | 11 | 00 | 010100 | 0xF14 | MHARTID | R | Hardware Thread ID |
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+-------+-----+-----+--------+--------+---------+--------+-----------------------------------+
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+---------+--------------------+--------+-----------------------------------------------+
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| Address | Name | Access | Description |
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+=========+====================+========+===============================================+
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| 0x300 | ``mstatus`` | RW | Machine Status |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0x301 | ``misa`` | WARL | Machine ISA and Extensions |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0x305 | ``mtvec`` | WARL | Machine Trap-Handler Base Address |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0x320 | ``mcountinhibit`` | RW | Machine Counter-Inhibit Register |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0x323 | ``mhpmevent3`` | WARL | Machine Performance-Monitoring Event Selector |
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+---------+--------------------+--------+-----------------------------------------------+
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| . . . . |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0x33F | ``mhpmevent31`` | WARL | Machine performance-monitoring event selector |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0x341 | ``mepc`` | RW | Machine Exception Program Counter |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0x342 | ``mcause`` | RW | Machine Trap Cause |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0x7B0 | ``dcsr`` | RW | Debug Control and Status Register |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0x7B1 | ``dpc`` | RW | Debug PC |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0x7B2 | ``dscratch0`` | RW | Debug Scratch Register 0 |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0x7B3 | ``dscratch1`` | RW | Debug Scratch Register 1 |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0xB00 | ``mcycle`` | RW | Machine Cycle Counter |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0xB02 | ``minstret`` | RW | Machine Instructions-Retired Counter |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0xB03 | ``mhpmcounter3`` | WARL | Machine Performance-Monitoring Counter |
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+---------+--------------------+--------+-----------------------------------------------+
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| . . . . |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0xB1F | ``mhpmcounter31`` | WARL | Machine Performance-Monitoring Counter |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0xB80 | ``mcycleh`` | RW | Upper 32 bits of ``mcycle`` |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0xB82 | ``minstreth`` | RW | Upper 32 bits of ``minstret`` |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0xB83 | ``mhpmcounter3h`` | WARL | Upper 32 bits of ``mhmpcounter3`` |
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+---------+--------------------+--------+-----------------------------------------------+
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| . . . . |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0xB9F | ``mhpmcounter31h`` | WARL | Upper 32 bits of ``mhmpcounter31`` |
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+---------+--------------------+--------+-----------------------------------------------+
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| 0xF14 | ``mhartid`` | R | Hardware Thread ID |
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+---------+--------------------+--------+-----------------------------------------------+
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Machine Status (MSTATUS)
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Machine Status (mstatus)
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------------------------
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CSR Address: ``0x300``
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@ -43,35 +70,37 @@ Reset Value: ``0x0000_1800``
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+-------+-----+------------------------------------------------------------------+
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| 12:11 | R | **MPP:** Statically 2’b11 and cannot be altered (read-only). |
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+-------+-----+------------------------------------------------------------------+
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| 7 | R/W | **Previous Interrupt Enable:** When an exception is encountered, |
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| 7 | RW | **Previous Interrupt Enable:** When an exception is encountered, |
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| | | MPIE will be set to IE. When the mret instruction is executed, |
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| | | the value of MPIE will be stored to IE. |
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+-------+-----+------------------------------------------------------------------+
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| 3 | R/W | **Interrupt Enable:** If you want to enable interrupt handling |
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| 3 | RW | **Interrupt Enable:** If you want to enable interrupt handling |
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| | | in your exception handler, set the Interrupt Enable to 1’b1 |
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| | | inside your handler code. |
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+-------+-----+------------------------------------------------------------------+
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Machine Trap-Vector Base Address (MTVEC)
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Machine Trap-Vector Base Address (mtvec)
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----------------------------------------
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CSR Address: ``0x305``
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When an exception is encountered, the core jumps to the corresponding handler using the content of the MTVEC as base address. It is a read-only register which contains the boot address.
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When an exception is encountered, the core jumps to the corresponding handler using the content of the ``mtvec`` as base address.
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It is a read-only register which contains the boot address.
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Machine Exception PC (MEPC)
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Machine Exception PC (mepc)
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---------------------------
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CSR Address: ``0x341``
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Reset Value: ``0x0000_0000``
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When an exception is encountered, the current program counter is saved in MEPC, and the core jumps to the exception address. When an mret instruction is executed, the value from MEPC replaces the current program counter.
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When an exception is encountered, the current program counter is saved in ``mepc``, and the core jumps to the exception address.
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When an ``mret`` instruction is executed, the value from ``mepc`` replaces the current program counter.
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Machine Cause (MCAUSE)
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Machine Cause (mcause)
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----------------------
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CSR Address: ``0x342``
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@ -90,8 +119,8 @@ Reset Value: ``0x0000_0000``
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.. _csr-mhartid:
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MHARTID
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-------
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Hardware Thread ID (mhartid)
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----------------------------
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CSR Address: ``0xF14``
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@ -8,73 +8,73 @@ Instantiation Template
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.. code-block:: verilog
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ibex_core
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#(.N_EXT_PERF_COUNTERS (0),
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.RV32E (0),
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.RV32M (1),
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.DM_HALT_ADDRESS(32'h1A110800),
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.DM_EXCEPTION_ADDRESS(32'h1A110808))
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u_core
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(// Clock and reset
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.clk_i (),
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.rst_ni (),
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.test_en_i (),
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ibex_core #(
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.NumMHPMCounters (8),
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.WidthMHPMCounters (40),
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.RV32E (0),
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.RV32M (1),
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.DmHaltAddr (32'h1A110800),
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.DmExceptionAddr (32'h1A110808)
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) u_core (
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// Clock and reset
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.clk_i (),
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.rst_ni (),
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.test_en_i (),
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// Configuration
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.core_id_i (),
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.cluster_id_i (),
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.boot_addr_i (),
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// Configuration
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.core_id_i (),
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.cluster_id_i (),
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.boot_addr_i (),
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// Instruction memory interface
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.instr_req_o (),
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.instr_gnt_i (),
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.instr_rvalid_i (),
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.instr_addr_o (),
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.instr_rdata_i (),
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// Instruction memory interface
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.instr_req_o (),
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.instr_gnt_i (),
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.instr_rvalid_i (),
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.instr_addr_o (),
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.instr_rdata_i (),
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// Data memory interface
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.data_req_o (),
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.data_gnt_i (),
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.data_rvalid_i (),
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.data_we_o (),
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.data_be_o (),
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.data_addr_o (),
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.data_wdata_o (),
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.data_rdata_i (),
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.data_err_i (),
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// Data memory interface
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.data_req_o (),
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.data_gnt_i (),
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.data_rvalid_i (),
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.data_we_o (),
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.data_be_o (),
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.data_addr_o (),
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.data_wdata_o (),
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.data_rdata_i (),
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.data_err_i (),
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// Interrupt inputs
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.irq_i (),
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.irq_id_i (),
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.irq_ack_o (),
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.irq_id_o (),
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// Interrupt inputs
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.irq_i (),
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.irq_id_i (),
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.irq_ack_o (),
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.irq_id_o (),
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// Debug Interface
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.debug_req_i (),
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// Debug Interface
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.debug_req_i (),
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// Special control signal
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.fetch_enable_i (),
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// External performance counters
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.ext_perf_counters_i ()
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);
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// Special control signal
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.fetch_enable_i ()
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);
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Parameters
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----------
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+--------------------------+-------------+------------+-----------------------------------------------------------------+
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| Name | Type/Range | Default | Description |
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+==========================+=============+============+=================================================================+
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| ``N_EXT_PERF_COUNTERS`` | int (0..21) | 0 | Number of external performance counters |
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+--------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``RV32E`` | bit | 0 | RV32E mode enable (16 integer registers only) |
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+--------------------------+-------------+------------+-----------------------------------------------------------------+
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| ``RV32M`` | bit | 1 | M(ultiply) extension enable |
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+-------------------------+--------------+------------+-----------------------------------------------------------------+
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| ``DM_HALT_ADDRESS`` | int | 0x1A110800 | Address to jump to when entering debug mode |
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+-------------------------+---------------------------------------------------------------------------------------------+
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| ``DM_EXCEPTION_ADDRESS`` | int | 0x1A110808 | Address to jump to when an exception occurs while in debug mode |
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+--------------------------+--------------------------------------------------------------------------------------------+
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+-----------------------+-------------+------------+-----------------------------------------------------------------+
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| Name | Type/Range | Default | Description |
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+=======================+=============+============+=================================================================+
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| ``NumMHPMCounters`` | int (0..29) | 8 | Number of performance monitor event counters |
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+-----------------------+-------------+------------+-----------------------------------------------------------------+
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| ``WidthMHPMCounters`` | int (64..32)| 40 | Bit width of performance monitor event counters |
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+-----------------------+-------------+------------+-----------------------------------------------------------------+
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| ``RV32E`` | bit | 0 | RV32E mode enable (16 integer registers only) |
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+-----------------------+-------------+------------+-----------------------------------------------------------------+
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| ``RV32M`` | bit | 1 | M(ultiply) extension enable |
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+-----------------------+-------------+------------+-----------------------------------------------------------------+
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| ``DmHaltAddr`` | int | 0x1A110800 | Address to jump to when entering debug mode |
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+-----------------------+-------------+------------+-----------------------------------------------------------------+
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| ``DmExceptionAddr`` | int | 0x1A110808 | Address to jump to when an exception occurs while in debug mode |
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+-----------------------+-------------+------------+-----------------------------------------------------------------+
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Interfaces
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@ -90,7 +90,7 @@ Interfaces
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``test_en_i`` | 1 | in | Test input, enables clock |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``core_id_i`` | 4 | in | Core id, usually static, can be read |
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| ``core_id_i`` | 4 | in | Core ID, usually static, can be read |
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| | | | from :ref:`csr-mhartid` |
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+-------------------------+-------------------------+-----+ +
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| ``cluster_id_i`` | 6 | in | |
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@ -107,5 +107,3 @@ Interfaces
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``fetch_enable_i`` | 1 | in | Enable the core, won't fetch when 0 |
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+-------------------------+-------------------------+-----+----------------------------------------+
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| ``ext_perf_counters_i`` | ``N_EXT_PERF_COUNTERS`` | in | External performance counter |
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+-------------------------+-------------------------+-----+----------------------------------------+
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@ -3,144 +3,114 @@
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Performance Counters
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====================
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Performance Counters in Ibex are placed inside the Control and Status Registers and can be accessed with csrr and csrw instructions.
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Ibex implements performance counters according to the RISC-V Privileged Specification, draft version 1.11 (see Hardware Performance Monitor, Section 3.1.11).
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The performance counters are placed inside the Control and Status Registers (CSRs) and can be accessed with the ``CSRRW(I)`` and ``CSRRS/C(I)`` instructions.
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Ibex implements the clock cycle counter ``mcycle(h)``, the retired instruction counter ``minstret(h)``, as well as the 29 event counters ``mhpmcounter3(h)`` - ``mhpmcounter31(h)`` and the corresponding event selector CSRs ``mhpmevent3`` - ``mhpmevent31``, and the ``mcountinhibit`` CSR to individually enable/disable the counters.
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Performance Counter Mode Register (PCMR)
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----------------------------------------
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Event Selector
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--------------
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CSR Address: ``0x7A1``
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The following events can be monitored using the performance counters of Ibex.
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Reset Value: ``0x0000_0003``
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+--------------+------------------+---------------------------------------------------------+
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| Event ID/Bit | Event Name | Event Description |
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+==============+==================+=========================================================+
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| 0 | NumCycles | Number of cycles |
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+--------------+------------------+---------------------------------------------------------+
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| 2 | NumInstrRet | Number of instructions retired |
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+--------------+------------------+---------------------------------------------------------+
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| 3 | NumCyclesLSU | Number of cycles waiting for data memory |
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+--------------+------------------+---------------------------------------------------------+
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| 4 | NumCyclesIF | Cycles waiting for instruction fetches, i.e., number of |
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| | | instructions wasted due to non-ideal caching |
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+--------------+------------------+---------------------------------------------------------+
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| 5 | NumLoads | Number of data memory loads. Misaligned accesses are |
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| | | counted as two accesses |
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+--------------+------------------+---------------------------------------------------------+
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| 6 | NumStores | Number of data memory stores. Misaligned accesses are |
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| | | counted as two accesses |
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+--------------+------------------+---------------------------------------------------------+
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| 7 | NumJumps | Number of unconditional jumps (j, jal, jr, jalr) |
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+--------------+------------------+---------------------------------------------------------+
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| 8 | NumBranches | Number of branches (conditional) |
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+--------------+------------------+---------------------------------------------------------+
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| 9 | NumBranchesTaken | Number of taken branches (conditional) |
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+--------------+------------------+---------------------------------------------------------+
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| 10 | NumInstrRetC | Number of compressed instructions retired |
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+--------------+------------------+---------------------------------------------------------+
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+-------+-----+------------------------------------------------------------------+
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| Bit# | R/W | Description |
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+=======+=====+==================================================================+
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| 0 | R/W | **Global Enable:** Activate/deactivate all performance counters. |
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| | | If this bit is 0, all performance counters are disabled. After |
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| | | reset, this bit is set. |
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+-------+-----+------------------------------------------------------------------+
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| 1 | R/W | **Saturation:** If this bit is set, saturating arithmetic is |
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| | | used in the performance counter counters. After reset, this bit |
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| | | is set. |
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+-------+-----+------------------------------------------------------------------+
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The event selector CSRs ``mhpmevent3`` - ``mhpmevent31`` define which of these events are counted by the event counters ``mhpmcounter3(h)`` - ``mhpmcounter31(h)``.
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If a specific bit in an event selector CSR is set to 1, this means that events with this ID are being counted by the counter associated with that selector CSR.
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If an event selector CSR is 0, this means that the corresponding counter is not counting any event.
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Counter Control
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---------------
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Performance Counter Event Register (PCER)
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-----------------------------------------
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By default, all available counters are enabled after reset.
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They can be individually enabled/disabled by overwriting the corresponding bit in the ``mcountinhibit`` CSR at address ``0x320`` as described in the RISC-V Privileged Specification, draft version 1.11 (see Machine Counter-Inhibit CSR, Section 3.1.13).
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In particular, to enable/disable ``mcycle(h)``, bit 0 must be written. For ``minstret(h)``, it is bit 2. For event counter ``mhpmcounterX(h)``, it is bit X.
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CSR Address: ``0x7A0``
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The lower 32 bits of all counters can be accessed through the base register, whereas the upper 32 bits are accessed through the ``h``-register.
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Reads to all these registers are non-destructive.
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Reset Value: ``0x0000_0000``
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Counter Config
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--------------
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+-------+-----+------------------------------------------------------------------+
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| Bit# | R/W | Description |
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+=======+=====+==================================================================+
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| 16 | R/W | **TCDM_CONT** |
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+-------+-----+------------------------------------------------------------------+
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| 15 | R/W | **ST_EXT_CYC** |
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+-------+-----+------------------------------------------------------------------+
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| 14 | R/W | **LD_EXT_CYC** |
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+-------+-----+------------------------------------------------------------------+
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| 13 | R/W | **ST_EXT** |
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+-------+-----+------------------------------------------------------------------+
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| 12 | R/W | **LD_EXT** |
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+-------+-----+------------------------------------------------------------------+
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| 11 | R/W | **DELAY_SLOT** |
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+-------+-----+------------------------------------------------------------------+
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| 10 | R/W | **BRANCH** |
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+-------+-----+------------------------------------------------------------------+
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| 9 | R/W | **JUMP** |
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+-------+-----+------------------------------------------------------------------+
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| 8 | R/W | **ST** |
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+-------+-----+------------------------------------------------------------------+
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| 7 | R/W | **LD** |
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+-------+-----+------------------------------------------------------------------+
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| 6 | R/W | **WBRANCH_CYC** |
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+-------+-----+------------------------------------------------------------------+
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| 5 | R/W | **WBRANCH** |
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+-------+-----+------------------------------------------------------------------+
|
||||
| 4 | R/W | **IMISS** |
|
||||
+-------+-----+------------------------------------------------------------------+
|
||||
| 3 | R/W | **RESERVED** |
|
||||
+-------+-----+------------------------------------------------------------------+
|
||||
| 2 | R/W | **RESERVED** |
|
||||
+-------+-----+------------------------------------------------------------------+
|
||||
| 1 | R/W | **INSTR** |
|
||||
+-------+-----+------------------------------------------------------------------+
|
||||
| 0 | R/W | **CYCLES** |
|
||||
+-------+-----+------------------------------------------------------------------+
|
||||
The ``mcycle(h)`` and ``minstret(h)`` counters are 64 bit wide.
|
||||
The bit width of the event counters ``mhpmcounter3(h)`` - ``mhpmcounter31(h)`` can be controlled via the ``WidthMHPMCounters`` parameter.
|
||||
|
||||
Each bit in the PCER register controls one performance counter. If the bit is 1, the counter is enabled and starts counting events. If it is 0, the counter is disabled and its value won’t change.
|
||||
The effective number of available event counters ``mhpmcounterX(h)`` can be controlled via the ``NumMHPMCounters`` parameter.
|
||||
By default, only the first 8 counters ``mhpmcounter3(h)`` - ``mhpmcounter10(h)`` are available.
|
||||
The association of events with these counters is hardwired as listed in the following table.
|
||||
The remaining counters are disabled and tied to 0.
|
||||
|
||||
In the ASIC there is only one counter register, thus all counter events are masked by PCER and ORed together, i.e. if one of the enabled event happens, the counter will be increased. If multiple non-masked events happen at the same time, the counter will only be increased by one.
|
||||
In order to be able to count separate events on the ASIC, the program can be executed in a loop with different events configured.
|
||||
+----------------------+----------------+--------------+------------------+
|
||||
| Event Counter | CSR Address | Event ID/Bit | Event Name |
|
||||
+======================+================+==============+==================+
|
||||
| ``mcycle(h)`` | 0xB00 (0xB80) | 0 | NumCycles |
|
||||
+----------------------+----------------+--------------+------------------+
|
||||
| ``minstret(h)`` | 0xB02 (0xB82) | 2 | NumInstrRet |
|
||||
+----------------------+----------------+--------------+------------------+
|
||||
| ``mhpmcounter3(h)`` | 0xB03 (0xB83) | 3 | NumCyclesLSU |
|
||||
+----------------------+----------------+--------------+------------------+
|
||||
| ``mhpmcounter4(h)`` | 0xB04 (0xB84) | 4 | NumCyclesIF |
|
||||
| | | | |
|
||||
+----------------------+----------------+--------------+------------------+
|
||||
| ``mhpmcounter5(h)`` | 0xB05 (0xB85) | 5 | NumLoads |
|
||||
| | | | |
|
||||
+----------------------+----------------+--------------+------------------+
|
||||
| ``mhpmcounter6(h)`` | 0xB06 (0xB86) | 6 | NumStores |
|
||||
| | | | |
|
||||
+----------------------+----------------+--------------+------------------+
|
||||
| ``mhpmcounter7(h)`` | 0xB07 (0xB87) | 7 | NumJumps |
|
||||
+----------------------+----------------+--------------+------------------+
|
||||
| ``mhpmcounter8(h)`` | 0xB08 (0xB88) | 8 | NumBranches |
|
||||
+----------------------+----------------+--------------+------------------+
|
||||
| ``mhpmcounter9(h)`` | 0xB09 (0xB89) | 9 | NumBranchesTaken |
|
||||
+----------------------+----------------+--------------+------------------+
|
||||
| ``mhpmcounter10(h)`` | 0xB0A (0xB8A) | 10 | NumInstrRetC |
|
||||
+----------------------+----------------+--------------+------------------+
|
||||
|
||||
In the FPGA or RTL simulation version, each event has its own counter and can be accessed separately.
|
||||
Similarly, the event selector CSRs are hardwired as follows.
|
||||
The remaining event selector CSRs are tied to 0, i.e., no events are counted by the corresponding counters.
|
||||
|
||||
Performance Counter Counter Register (PCCR0-31)
|
||||
-----------------------------------------------
|
||||
|
||||
CSR Address: ``0x780`` - ``0x79F``
|
||||
|
||||
Reset Value: ``0x0000_0000``
|
||||
|
||||
PCCR registers support both saturating and wrap-around arithmetic. This is controlled by the saturation bit in PCMR.
|
||||
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| Register | Name | Description |
|
||||
+==========+================+================================================================+
|
||||
| PCCR0 | **CYCLES** | Counts the number of cycles the core was active (not sleeping) |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR1 | **INSTR** | Counts the number of instructions executed |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR2 | **-** | Reserved |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR3 | **-** | Reserved |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR4 | **IMISS** | Cycles waiting for instruction fetches, i.e. number of |
|
||||
| | | instructions wasted due to non-ideal caching |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR5 | **LD** | Number of data memory loads executed. Misaligned accesses are |
|
||||
| | | counted twice |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR6 | **ST** | Number of data memory stores executed. Misaligned accesses are |
|
||||
| | | counted twice |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR7 | **JUMP** | Number of unconditional jumps (j, jal, jr, jalr) |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR8 | **BRANCH** | Number of branches. Counts taken and not taken branches |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR9 | **BTAKEN** | Number of taken branches. |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR10 | **RVC** | Number of compressed instructions executed |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR11 | **LD_EXT** | Number of memory loads to EXT executed. Misaligned accesses |
|
||||
| | | are counted twice. Every non-TCDM access is considered |
|
||||
| | | external (PULP only) |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR12 | **ST_EXT** | Number of memory stores to EXT executed. Misaligned accesses |
|
||||
| | | are counted twice. Every non-TCDM access is considered |
|
||||
| | | external (PULP only) |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR13 | **LD_EXT_CYC** | Cycles used for memory loads to EXT. Every non-TCDM access is |
|
||||
| | | considered external (PULP only) |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR14 | **ST_EXT_CYC** | Cycles used for memory stores to EXT. Every non-TCDM access is |
|
||||
| | | considered external (PULP only) |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR15 | **TCDM_CONT** | Cycles wasted due to TCDM/log-interconnect contention |
|
||||
| | | (PULP only) |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
| PCCR31 | **ALL** | Special Register, a write to this register will set all |
|
||||
| | | counters to the supplied value |
|
||||
+----------+----------------+----------------------------------------------------------------+
|
||||
|
||||
In the FPGA, RTL simulation and Virtual-Platform there are individual counters for each event type, i.e. PCCR0-30 each represent a separate register. To save area in the ASIC, there is only one counter and one counter register. Accessing PCCR0-30 will access the same counter register in the ASIC. Reading/writing from/to PCCR31 in the ASIC will access the same register as PCCR0-30.
|
||||
|
||||
:numref:`pcer` shows how events are first masked with the PCER register and then ORed together to increase the one performance counter PCCR.
|
||||
|
||||
.. figure:: images/pcer.png
|
||||
:name: pcer
|
||||
|
||||
Events and PCCR, PCMR and PCER on the ASIC.
|
||||
+----------------------+-------------+-------------+--------------+
|
||||
| Event Selector | CSR Address | Reset Value | Event ID/Bit |
|
||||
+======================+=============+=============+==============+
|
||||
| ``mhpmevent3(h)`` | 0x323 | 0x0000_0008 | 3 |
|
||||
+----------------------+-------------+-------------+--------------+
|
||||
| ``mhpmevent4(h)`` | 0x324 | 0x0000_0010 | 4 |
|
||||
+----------------------+-------------+-------------+--------------+
|
||||
| ``mhpmevent5(h)`` | 0x325 | 0x0000_0020 | 5 |
|
||||
+----------------------+-------------+-------------+--------------+
|
||||
| ``mhpmevent6(h)`` | 0x326 | 0x0000_0040 | 6 |
|
||||
+----------------------+-------------+-------------+--------------+
|
||||
| ``mhpmevent7(h)`` | 0x327 | 0x0000_0080 | 7 |
|
||||
+----------------------+-------------+-------------+--------------+
|
||||
| ``mhpmevent8(h)`` | 0x328 | 0x0000_0100 | 8 |
|
||||
+----------------------+-------------+-------------+--------------+
|
||||
| ``mhpmevent9(h)`` | 0x329 | 0x0000_0200 | 9 |
|
||||
+----------------------+-------------+-------------+--------------+
|
||||
| ``mhpmevent10(h)`` | 0x32A | 0x0000_0400 | 10 |
|
||||
+----------------------+-------------+-------------+--------------+
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue