[ci] Add clang-format checking to CI

- Only checks changed C source files
- Also add a note on C/C++ style to README
- Fixes #304

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>

README.md

@@ -40,6 +40,11 @@ please:
 When contributing SystemVerilog source code, please try to be consistent and adhere to [our Verilog
 coding style guide](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md).
 
+When contributing C or C++ source code, please try to adhere to [the OpenTitan C++ coding style
+guide](https://docs.opentitan.org/doc/rm/c_cpp_coding_style/).
+All C and C++ code should be formatted with clang-format before committing.
+Either run `clang-format -i filename.cc` or `git clang-format` on added files.
+
 To get started, please check out the ["Good First Issue"
  list](https://github.com/lowrisc/ibex/issues?q=is%3Aissue+is%3Aopen+label%3A%22Good+First+Issue%22).
 

azure-pipelines.yml

@@ -46,6 +46,7 @@ jobs:
           bison \
           curl \
           libelf-dev \
+          clang-format \
         && sudo pip3 install -U six fusesoc
     displayName: Install dependencies
 
@@ -95,6 +96,20 @@ jobs:
       fi
     displayName: Lint Verilog source files with Verilator
 
+  - bash: |
+      fork_origin=$(git merge-base --fork-point origin/master)
+      changed_files=$(git diff --name-only $fork_origin | grep -v /vendor/ | grep -E '\.(cpp|cc|c|h)$')
+      test -z "$changed_files" || git diff -U0 $fork_origin $changed_files | clang-format-diff -p1 | tee clang-format-output
+      if [ -s clang-format-output ]; then
+        echo -n "##vso[task.logissue type=error]"
+        echo "C/C++ lint failed. Use 'git clang-format' with appropriate options to reformat the changed code."
+        exit 1
+      fi
+    # This check is not idempotent, but checks changes to a base branch.
+    # Run it only on pull requests.
+    condition: eq(variables['Build.Reason'], 'PullRequest')
+    displayName: 'Use clang-format to check C/C++ coding style'
+
   - bash: |
       # Build and run CSR testbench
       fusesoc --cores-root=. run --target=sim --tool=verilator lowrisc:ibex:tb_cs_registers