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[fcov] CSR related coverage points

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Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This commit is contained in:
Canberk Topal 2022-04-06 11:09:35 +01:00 • committed by Canberk Topal
parent 11002708ea
commit f21b6545ac
5 changed files with 69 additions and 7 deletions
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13
dv/uvm/core_ibex/fcov/core_ibex_csr_categories.svh
View file

@ -99,12 +99,7 @@
CSR_MHPMCOUNTER28H, \
CSR_MHPMCOUNTER29H, \
CSR_MHPMCOUNTER30H, \
CSR_MHPMCOUNTER31H, \
// Must exist when implementing hardware triggers (breakpoints), but read as 0 and ignore \
// writes. Unused/Uneeded by debugger infrastructure. \
// TODO: Don't ignore these? \
CSR_MCONTEXT, \
CSR_SCONTEXT
CSR_MHPMCOUNTER31H
// Debug related CSRs
`define DEBUG_CSRS \
@ -117,3 +112,9 @@
CSR_TDATA2, \
CSR_TDATA3
// Must exist when implementing hardware triggers (breakpoints), but read as 0 and ignore \
// writes. Unused/unneeded by debugger infrastructure. \
`define NOT_IMPLEMENTED_CSRS \
CSR_MCONTEXT, \
CSR_SCONTEXT, \
CSR_TDATA3

3
dv/uvm/core_ibex/fcov/core_ibex_fcov_bind.sv
View file

@ -9,7 +9,8 @@ module core_ibex_fcov_bind;
bind ibex_core core_ibex_pmp_fcov_if
#(.PMPGranularity(PMPGranularity),
.PMPNumRegions(PMPNumRegions))
.PMPNumRegions(PMPNumRegions),
.PMPEnable(PMPEnable))
u_pmp_fcov_bind (
.*
);

48
dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
View file

@ -349,6 +349,45 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
`DV_FCOV_EXPR_SEEN(mret_in_umode, id_stage_i.mret_insn_dec && priv_mode_id == PRIV_LVL_U)
`DV_FCOV_EXPR_SEEN(wfi_in_umode, id_stage_i.wfi_insn_dec && priv_mode_id == PRIV_LVL_U)
// Unsupported writes to WARL type CSRs
`DV_FCOV_EXPR_SEEN(warl_check_mstatus,
fcov_csr_write &&
(cs_registers_i.u_mstatus_csr.wr_data_i !=
cs_registers_i.csr_wdata_int))
`DV_FCOV_EXPR_SEEN(warl_check_mie,
fcov_csr_write &&
(cs_registers_i.u_mie_csr.wr_data_i !=
cs_registers_i.csr_wdata_int))
`DV_FCOV_EXPR_SEEN(warl_check_mtvec,
fcov_csr_write &&
(cs_registers_i.u_mtvec_csr.wr_data_i !=
cs_registers_i.csr_wdata_int))
`DV_FCOV_EXPR_SEEN(warl_check_mepc,
fcov_csr_write &&
(cs_registers_i.u_mepc_csr.wr_data_i !=
cs_registers_i.csr_wdata_int))
`DV_FCOV_EXPR_SEEN(warl_check_mtval,
fcov_csr_write &&
(cs_registers_i.u_mtval_csr.wr_data_i !=
cs_registers_i.csr_wdata_int))
`DV_FCOV_EXPR_SEEN(warl_check_dcsr,
fcov_csr_write &&
(cs_registers_i.u_dcsr_csr.wr_data_i !=
cs_registers_i.csr_wdata_int))
`DV_FCOV_EXPR_SEEN(warl_check_cpuctrl,
fcov_csr_write &&
(cs_registers_i.u_cpuctrl_csr.wr_data_i !=
cs_registers_i.csr_wdata_int))
`DV_FCOV_EXPR_SEEN(double_fault, cs_registers_i.cpuctrl_d.double_fault_seen)
`DV_FCOV_EXPR_SEEN(icache_enable, cs_registers_i.cpuctrl_d.icache_enable)
cp_irq_pending: coverpoint id_stage_i.irq_pending_i | id_stage_i.irq_nm_i;
cp_debug_req: coverpoint id_stage_i.controller_i.fcov_debug_req;
@ -360,6 +399,15 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
ignore_bins ignore = {`IGNORED_CSRS};
}
// All CSR operations perform a read so we don't need to specify the CSR operation.
cp_ignored_csrs: coverpoint cs_registers_i.csr_addr_i iff (id_stage_i.csr_access_o) {
bins unimplemented_csrs_read = {`NOT_IMPLEMENTED_CSRS};
}
cp_ignored_csrs_w: coverpoint cs_registers_i.csr_addr_i iff (fcov_csr_write) {
bins unimplemented_csrs_written = {`NOT_IMPLEMENTED_CSRS};
}
`DV_FCOV_EXPR_SEEN(csr_invalid_read_only, fcov_csr_read_only && cs_registers_i.illegal_csr)
`DV_FCOV_EXPR_SEEN(csr_invalid_write, fcov_csr_write && cs_registers_i.illegal_csr)

4
dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv
View file

@ -98,6 +98,10 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #(
covergroup pmp_region_cg @(posedge clk_i);
option.per_instance = 1;
option.name = "pmp_region_cg";
cp_warl_check_pmpcfg : coverpoint
g_pmp_fcov_signals.g_pmp_region_fcov[i_region].fcov_warl_check_pmpcfg;
cp_region_mode : coverpoint csr_pmp_cfg[i_region].mode;
cp_region_priv_bits : coverpoint pmp_region_priv_bits {

8
rtl/ibex_core.sv
View file

@ -1641,6 +1641,14 @@ module ibex_core import ibex_pkg::*; #(
g_pmp.pmp_i.region_match_all[PMP_I2][i_region] & if_stage_i.if_id_pipe_reg_we)
`DV_FCOV_SIGNAL(logic, pmp_region_dchan_access,
g_pmp.pmp_i.region_match_all[PMP_D][i_region] & data_req_out)
// pmp_cfg[5:6] is reserved and because of that the width of it inside cs_registers module
// is 6-bit.
// TODO: Cover writes to the reserved bits
`DV_FCOV_SIGNAL(logic, warl_check_pmpcfg,
fcov_csr_write &&
(cs_registers_i.g_pmp_registers.g_pmp_csrs[i_region].u_pmp_cfg_csr.wr_data_i !=
{cs_registers_i.csr_wdata_int[(i_region%4)*PMP_CFG_W+:5],
cs_registers_i.csr_wdata_int[(i_region%4)*PMP_CFG_W+7]}))
if (i_region > 0) begin : g_region_priority
assign fcov_pmp_region_ichan_priority[i_region] =