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[Prefetch buffer] - various bug fixes

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- Fix incorrect address output to mepc on interrupt (fixes #320)
- Fix instruction address changing before grant (fixes #296)
- Suppress requests and reg writes on fetch error (fixes #340)
- Remove excess address flops in fetch_fifo
- Remove restriction on outstanding requests
This commit is contained in:
Tom Roberts 2019-09-18 15:37:42 +01:00 • committed by Tom Roberts
parent b03ae4e2a7
commit f2fccaadbc
7 changed files with 151 additions and 148 deletions
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6
lint/verilator_waiver.vlt
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@ -56,15 +56,15 @@ lint_off -msg UNUSED -file "*/rtl/ibex_pmp.sv" -lines 16
// Signal is not used: csr_pmp_addr
// Signal not connected when PMP is not configured
lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 185
lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 186
// Signal is not used: csr_pmp_cfg
// Signal not connected when PMP is not configured
lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 186
lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 187
// Signal is not used: priv_mode
// Signal not connected when PMP is not configured
lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 198
lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 199
// Signal unoptimizable: Feedback to clock or circular logic:
// ibex_core.id_stage_i.controller_i.ctrl_fsm_cs