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[dv] Add cpuctrlsts writes to riscv_rand_instr_test

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This will have the effect of randomly enabling/disabling

 - The ICache
 - Dummy instruction insertion
 - Data independent timing
This commit is contained in:
Greg Chadwick 2022-09-09 18:55:07 +01:00 • committed by Greg Chadwick
parent a0fe5ea3b7
commit f385d4d6b1
1 changed files with 1 additions and 1 deletions
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2
dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
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@ -36,7 +36,7 @@
+instr_cnt=10000
+num_of_sub_program=5
+gen_all_csrs_by_default=1
+add_csr_write=MSTATUS,MEPC,MCAUSE,MTVAL
+add_csr_write=MSTATUS,MEPC,MCAUSE,MTVAL,0x7c0
+no_csr_instr=0
rtl_test: core_ibex_base_test