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Improve wording in README of simple system

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Small editorial fixes.
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Philipp Wagner 2020-01-23 17:30:17 +00:00 • committed by Philipp Wagner
parent 2ef34b6d05
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37
examples/simple_system/README.md
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@ -15,7 +15,7 @@ run stand-alone binaries. It contains:
Note Linux package managers may have Verilator but often a very old version
that is not suitable. It is recommended Verilator is built from source.
* [FuseSoC](https://github.com/olofk/fusesoc)
* RISC-V Compiler Toolchain - lowRISC provides a pre-built GCC based toolchain
* RISC-V Compiler Toolchain - lowRISC provides a pre-built GCC based toolchain
<https://github.com/lowRISC/lowrisc-toolchains/releases>
## Building Simulation
@ -29,7 +29,7 @@ fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple
## Building Software
Simple System related software can be found in examples/sw/simple_system
Simple System related software can be found in `examples/sw/simple_system`.
To build the hello world example, from the Ibex reposistory root run:
@ -38,14 +38,14 @@ make -C examples/sw/simple_system/hello_test
```
This should create the file
examples/sw/simple_system/hello_test/hello_test.vmem which is the memory
initialisation file used to run the hello_test program
`examples/sw/simple_system/hello_test/hello_test.vmem` which is the memory
initialisation file used to run the `hello_test` program.
To build new software make a copy of the hello_test directory named as desired.
To build new software make a copy of the `hello_test` directory named as desired.
Look inside the Makefile for further instructions.
If using a toolchain other than the lowRISC pre-built one
examples/sw/simple_system/common/common.mk may need altering to point to the
`examples/sw/simple_system/common/common.mk` may need altering to point to the
correct compiler binaries.
## Running the Simulator
@ -53,15 +53,16 @@ correct compiler binaries.
Having built the simulator and software, from the Ibex repository root run:
```
./build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system [-t] --raminit=<sw_vmem_file>
./build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system [-t] --meminit=ram,<sw_vmem_file>
```
`<sw_vmem_file>` should be a path to a vmem file built as described above, use
./examples/sw/simple_system/hello_test/hello_test.vmem to run the hello_test
`<sw_vmem_file>` should be a path to a Verilog memory (vmem) file, or an ELF
file built as described above. Use
`./examples/sw/simple_system/hello_test/hello_test.elf` to run the `hello_test`
binary.
Pass `-t` to get an FST trace of execution that be viewed with [GTKWave](http://gtkwave.sourceforge.net/)
If using the hello_test binary the simulator will halt itself, outputting some
If using the `hello_test` binary the simulator will halt itself, outputting some
simulation statistics:
```
@ -88,9 +89,9 @@ Compressed Instructions: 182
The simulator produces several output files
* ibex_simple_system.log - The ASCII output written via the output peripheral
* ibex_simple_system_pcount.csv - A csv of the performance counters
* trace_core_00000000.log - An instruction trace of execution
* `ibex_simple_system.log` - The ASCII output written via the output peripheral
* `ibex_simple_system_pcount.csv` - A csv of the performance counters
* `trace_core_00000000.log` - An instruction trace of execution
## Simulating with Synopsys VCS
@ -101,7 +102,7 @@ fusesoc --cores-root=. run --target=sim --tool=vcs --setup --build lowrisc:ibex:
```
`<sw_vmem_file>` should be a path to a vmem file built as described above, use
./examples/sw/simple_system/hello_test/hello_test.vmem to run the hello_test
`./examples/sw/simple_system/hello_test/hello_test.vmem` to run the `hello_test`
binary.
To run the simulator:
@ -118,9 +119,9 @@ Pass `-gui` to use the DVE GUI.
|---------------------|--------------------------------------------------------------------------------------------------------|
| 0x20000 | ASCII Out, write ASCII characters here that will get output to the log file |
| 0x20004 | Simulator Halt, write 1 here to halt the simulation |
| 0x30000 | RISCV timer mtime register |
| 0x30004 | RISCV timer mtimeh register |
| 0x30008 | RISCV timer mtimecmp register |
| 0x3000C | RISCV timer mtimecmph register |
| 0x30000 | RISC-V timer `mtime` register |
| 0x30004 | RISC-V timer `mtimeh` register |
| 0x30008 | RISC-V timer `mtimecmp` register |
| 0x3000C | RISC-V timer `mtimecmph` register |
| 0x100000 – 0x1FFFFF | 1 MB memory for instruction and data. Execution starts at 0x100080, exception handler base is 0x100000 |