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Fix time loop and some wrong eret address in controller

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This commit is contained in:
Markus Wegmann 2017-01-11 04:01:44 +01:00
parent b6829445c9
commit fc1bb02a73
1 changed files with 1 additions and 4 deletions
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5
controller.sv
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@ -404,7 +404,7 @@ module riscv_controller
pc_set_o = 1'b1;
exc_ack_o = 1'b1;
exc_save_id_o = 1'b1;
exc_save_if_o = 1'b1;
// we don't have to change our current state here as the prefetch
// buffer is automatically invalidated, thus the next instruction
@ -474,7 +474,6 @@ module riscv_controller
pc_mux_o = PC_EXCEPTION;
pc_set_o = 1'b1;
exc_ack_o = 1'b1;
halt_id_o = 1'b1; // we don't want to propagate this instruction to EX
exc_save_if_o = 1'b1;
// we don't have to change our current state here as the prefetch
// buffer is automatically invalidated, thus the next instruction
@ -534,8 +533,6 @@ module riscv_controller
pc_mux_o = PC_EXCEPTION;
pc_set_o = 1'b1;
exc_ack_o = 1'b1;
halt_id_o = 1'b1; // we don't want to propagate this instruction to EX
exc_save_id_o = 1'b1;
// we don't have to change our current state here as the prefetch