[dv] Don't inject mem errors at test_control_addr

This will prevent seeing mismatches right at the end of our test.
Before this change, mem_error_test could inject error at the store
instruction in which we finish up the test, resulting with mismatches
with Spike and Ibex on the instructions after finishing.

Also do the same prevention for signature_addr as well, since we also
don't want to corrupt that memory transaction too.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>

dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv

@@ -61,7 +61,12 @@ class ibex_mem_intf_response_seq extends uvm_sequence #(ibex_mem_intf_seq_item);
       end
       error_synch = 1'b1;
       enable_error = 1'b0; // Disable after single inserted error.
-
+      aligned_addr = {req.addr[DATA_WIDTH-1:2], 2'b0};
+      // Do not inject any error to the handshake test_control_addr
+      // TODO: Parametrize this. Until then, this needs to be changed manually.
+      if (aligned_addr inside {32'h8ffffff8, 32'h8ffffffc}) begin
+        req.error = 1'b0;
+      end
       if (req.error) begin
         `DV_CHECK_STD_RANDOMIZE_FATAL(rand_data)
         req.data = rand_data;