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[rtl] disable clock between reset and fetch_enable_i

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Fixes lowRISC#957

Signed-off-by: Bert Pieters <bert.pieters@gmail.com>
This commit is contained in:
Bert Pieters 2020-06-19 10:09:44 +02:00 • committed by Pirmin Vogel
parent a247cd45e9
commit fdfdcc0467
3 changed files with 11 additions and 9 deletions
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6
rtl/ibex_controller.sv
View file

@ -15,7 +15,6 @@ module ibex_controller #(
input logic clk_i,
input logic rst_ni,
input logic fetch_enable_i, // start decoding
output logic ctrl_busy_o, // core is busy processing instrs
// decoder related signals
@ -396,14 +395,11 @@ module ibex_controller #(
unique case (ctrl_fsm_cs)
RESET: begin
// just wait for fetch_enable
instr_req_o = 1'b0;
pc_mux_o = PC_BOOT;
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
if (fetch_enable_i) begin
ctrl_fsm_ns = BOOT_SET;
end
ctrl_fsm_ns = BOOT_SET;
end
BOOT_SET: begin

12
rtl/ibex_core.sv
View file

@ -353,8 +353,17 @@ module ibex_core #(
core_busy_q <= core_busy_d;
end
end
// capture fetch_enable_i in fetch_enable_q, once for ever
logic fetch_enable_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
fetch_enable_q <= 1'b0;
end else if (fetch_enable_i) begin
fetch_enable_q <= 1'b1;
end
end
assign clock_en = core_busy_q | debug_req_i | irq_pending | irq_nm_i;
assign clock_en = fetch_enable_q & (core_busy_q | debug_req_i | irq_pending | irq_nm_i);
assign core_sleep_o = ~clock_en;
// main clock gate of the core
@ -460,7 +469,6 @@ module ibex_core #(
.rst_ni ( rst_ni ),
// Processor Enable
.fetch_enable_i ( fetch_enable_i ),
.ctrl_busy_o ( ctrl_busy ),
.illegal_insn_o ( illegal_insn_id ),

2
rtl/ibex_id_stage.sv
View file

@ -28,7 +28,6 @@ module ibex_id_stage #(
input logic clk_i,
input logic rst_ni,
input logic fetch_enable_i,
output logic ctrl_busy_o,
output logic illegal_insn_o,
@ -526,7 +525,6 @@ module ibex_id_stage #(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.fetch_enable_i ( fetch_enable_i ),
.ctrl_busy_o ( ctrl_busy_o ),
// decoder related signals