Commit graph

4 commits

Author SHA1 Message Date
Tom Roberts
44b033cf8b [rtl] Add support for instruction fetch errors
- Add required signals to top-level
- Propagate error through fetch stages
- Add new exception type
- Update documentation for new exception type
- Resolves issue #109
2019-08-09 10:44:37 +01:00
Pirmin Vogel
1aa276dbc0 RVFI: re-add accidentally removed rvfi_intr signal
This signal is now set during the first instruction after the PC has
been set to enter a trap handler.
2019-07-26 09:30:45 +01:00
Pirmin Vogel
0dee0ff1ec Adapt interrupt IF for Arty example, tracer and TB 2019-07-24 18:58:26 +01:00
Philipp Wagner
62f3573f2b Rework how tracer is instantiated and called
This change is slighly painful, but a necessary cleanup around the
tracer.

- We now provide a separate core file for the tracer, called
  "ibex_tracer.core" (in line with "ibex_tracer.sv"). The core is called
  "lowrisc:ibex:ibex_tracer".
- The toplevel wrapper with tracing enabled got renamed to
  "ibex_core_tracing.sv", and the core file is correspondingly called
  "ibex_core_tracing.core. The core in it is called
  "lowrisc:ibex:ibex_core_tracing".
- Finally to keep symmetry, the toplevel of Ibex itself got renamed in
  the core file from "lowrisc:ibex:ibex" to "lowrisc:ibex:ibex_core".
  This ensures that we have the same name for the core file, the source
  entry point, and the core name.

IMPORTANT NOTE:
If you apply this change and use fusesoc, you need to adjust the name of
the core dependency from "lowrisc:ibex:ibex" to
"lowrisc:ibex:ibex_core".
2019-07-23 19:45:48 +01:00
Renamed from rtl/ibex_core_tracer.sv (Browse further)