Commit graph

25 commits

Author SHA1 Message Date
Pirmin Vogel
28935490c2 [rtl] Protect core_busy_o with a multi-bit encoding
This commit protects the core_busy_o signal using a multi-bit encoding
to reduce the chances of an adversary for glitching this signal to low,
thereby putting the core to sleep and e.g. not handling an alert.

Without this commit, the glitch would only be detected once both the
main core and the shadow core wake up again and the comparison of the
core_busy_o signals continues.

This resolves lowRISC/Ibex#1827.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2022-10-25 12:52:01 +02:00
Greg Chadwick
27907d1d4a [rtl] Immediately stop execution when fetch disabled
Previously `fetch_enable_i` only controlled the request going into the
instruction fetch stage.  Due to buffering in the prefetch queue and
icache when this request is dropped it's possible for multiple
instructions to still be available for the ID/EX stage to consume. So
when `fetch_enable_i` was set to off you would get a 'soft stop'. Some
finite number of instructions may still execute and Ibex would come to
an eventual halt.

Now `fetch_enable_i` also gates the instruction moving between the fetch
stage and the ID/EX stage. This gives a 'hard stop' where once fetch is
disabled Ibex comes to an immediate halt.
2022-10-16 17:17:15 +01:00
nedguthrie
fe157648a6 Fix formatting if IcacheScramble Description 2022-05-20 20:29:04 +01:00
Greg Chadwick
b18eceba81 [rtl] Switch to multi-bit fetch enable
The multi-bit enable aids security hardening. For non secure Ibex all
but the bottom bit is ignored so it is effectively a single bit enable.
2022-02-21 15:35:35 +00:00
Rupert Swarbrick
302bb65161 [doc] Update bitmanip list in integration.rst 2022-02-17 16:19:59 +00:00
Greg Chadwick
9943f9a42c [rtl, doc] Seperate major alert into internal and bus
This is to allow more consistent signalling in systems that integrate
Ibex (e.g. OpenTitan) so bus integrity errors external to Ibex and one's
detected within Ibex can be fed into the same alert whilst seperating
out Ibex's various internal alert causes.
2022-02-17 15:11:51 +00:00
Rupert Swarbrick
4bcc0fae6a [doc] Fix botched table layout
My commit 46b7e07 moved the right-most pipe symbol, which causes
Sphinx to skip the rest of the file. Oops!
2022-02-02 10:19:13 +00:00
Rupert Swarbrick
46b7e07098 [doc] Fix RV32B enum description 2022-01-27 16:02:44 +00:00
Greg Chadwick
c0f67946f2 [rtl,doc] Add double fault detection.
Fixes #1117
2022-01-25 15:05:39 +00:00
Canberk Topal
187944c417 [icache] Add RAM Primitives for scrambling
This commit includes switching to a scrambling RAM primitive for
ICache data and tag RAMs. Also introduces minor changes to ICache
to handle scrambling key valid signal.

It also includes a minor bug fix regarding not initializing
`fill_way_q` signal without ResetAll parameter. When the parameter
is not set and we have our first hit right after ICache enables,
the signal hangs.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
2022-01-19 14:59:43 +00:00
Greg Chadwick
6815e7b714 [rtl] Implement mvendorid/marchid/mimpid CSRs 2021-08-31 17:39:01 +01:00
Tom Roberts
48f11c6733 [rtl] Add bus integrity checking
Extra bits are added alongside read/write data for the instruction and
data buses to facilitate data integrity checking.

Ibex testbench extended to generate the expected bits.

All other top-levels modified to add the new signals (which are mostly
ignored).

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-08-26 16:55:26 +01:00
Pirmin Vogel
14115ea3a8 [util] Document minimal requirement for Xilinx Vivado
This is related to lowRISC/Ibex#1425.
2021-08-26 14:42:26 +02:00
Tom Roberts
65bf9c94f9 [rtl] Add LFSR permutation option
Random constants are sent through the hierarchy as parameters in-line
with other OpenTitan modules.

Further detail on this mechanism can be found in lowrisc/opentitan#2229

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-08-10 16:13:02 +01:00
Tom Roberts
6daae3509a [rtl] Modify fetch_en_i behavior
This signal used to be a one shot enable out of reset. We need an option
to pause execution for OpenTitan, so fetch_enable is extended to cover
that.

The signal is already driven low by the testbench at the end of test.
This is moved after the performance counter reads to ensure they can
complete.

Fixes #1105

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-06-23 09:16:27 +01:00
Rupert Swarbrick
7ceff60749 Describe where to find a RISC-V toolchain 2021-06-08 15:41:02 +01:00
Tom Roberts
7ac218f3ae [rtl] Wire scan_rst_ni through ibex_top_tracing
Better to have the tracing top consistent with the non-tracing top.

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-04-21 12:41:24 +01:00
Timothy Chen
33cca5e127 [ibex] Add reset bypass controls
Signed-off-by: Timothy Chen <timothytim@google.com>
2021-04-21 09:14:12 +01:00
Tom Roberts
a88f5eb912 [rtl] Add dual core lockstep option
Note that the alert output is tied off for now until an option is added
to reset all registers (otherwise there will be X propagation).

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-04-07 12:07:38 +01:00
Tom Roberts
6a3200929b [rtl] Add a new top level plus wiring
This commit creates a new top level wrapping the core, register file and
icache RAMs. The tracing top level is also renamed to ibex_top_tracing
to match. This new top level is intended to enable a dual core lockstep
implementation of Ibex.

There are no functional changes in this commit, only wiring.

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-04-07 12:07:38 +01:00
Rupert Swarbrick
026db55c89 [util] Document required VCS version
We don't actually run anything that checks this at the moment, but at
least we now have it written down somewhere.
2021-04-06 14:13:22 +01:00
Tom Roberts
2c75c2b2ec Update lowrisc_ip to lowRISC/opentitan@1ae03937f
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
1ae03937f0bb4b146bb6e736bccb4821bfda556b

* [prim/fifo_async] Add assertions on pointers (Tom Roberts)
* [prim/fifo_async] Add support for Depth <= 2 (Tom Roberts)
* [prim/fifo_async] Code tidy-up (Tom Roberts)
* [top / ast] Continued ast integration (Timothy Chen)
* [dvsim] Use bash when running make underneath (Srikrishna Iyer)
* [prim] Increase maximum width for prim_util_memload to 312 (Greg
  Chadwick)
* [sram_ctrl] Fix potential back-to-back partial write bug (Michael
  Schaffner)
* [dvsim] Fix for lowRISC/opentitan#5527 (Srikrishna Iyer)
* [lint] Waive Verilator UNUSED warnings for packages (Rupert
  Swarbrick)
* [uvmdvgen] Update DV doc path and terminology (Srikrishna Iyer)
* [clkmgr] Fix dft issues (Timothy Chen)
* [util] add `dec` types to prim_secded_pkg (Udi Jonnalagadda)
* [util] minor updates to secded_gen (Udi Jonnalagadda)
* [lint] Fix a bunch of lint warnings related to long lines (>100
  chars) (Michael Schaffner)
* [dv] Update common intr_test seq (Weicai Yang)
* [util] Slight refactor of secded_gen.py (Timothy Chen)
* [tlul] Add memory transmission integrity checks (Timothy Chen)
* [dvsim] Move clean_odirs to `util.py` (Srikrishna Iyer)
* [dvsim] Split Deploy into Deploy and Launcher (Srikrishna Iyer)
* [dvsim] Add utils.TS_FORMAT* vars (Srikrishna Iyer)
* [dv/lock_reg] Update IPs to adopt the lock_reg changes (Cindy Chen)
* [dv/enable_regs] Support enable registers have more than one field
  (Cindy Chen)
* [dv/base_reg] use m_field instead of accessing field (Cindy Chen)
* [dv/sram] add SRAM scrambling model for DV (Udi Jonnalagadda)
* [dv/tools] Updated Coverage flow for xcelium (Rasmus Madsen)

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-03-12 16:15:22 +00:00
Tom Roberts
ee8d1051bb [rtl] Add crash dump outputs
Relates to lowrisc/opentitan#4618

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-03-01 10:12:04 +00:00
Tom Roberts
8953d82ca4 [rtl] Various security feature bugfixes
- Document that SecureIbex cannot be used without a multiplier and add
  an assertion in the rtl. This fixes #1080.
- Move the PC checking hardware onto its own parameter to match all the
  other individual security features.
- Make the PC increment behavior more sensible on fetch errors (and make
  it match the icache behavior). Factor this into the PC increment check
  to prevent false triggering, fixes #1094.
- Stop the PC mismatch checker firing on dummy instructions, fixes
  #1095.

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2020-10-14 15:46:10 +01:00
Philipp Wagner
830b7f7206 Restructure documentation
Restructure the existing documentation to group the content by intended
audience. This produces four sections:

* An introduction section, relevant to "newcomers" to Ibex.
* An user guide, intended for hardware designers (integrators) and
  software developers who want to integrate Ibex, and develop software
  for it.
* A reference guide, which provides background information on the
  design. This section is essential when working on Ibex, and also
  documents our design decisions.
* A developer guide aimed at people modifying Ibex itself. It consists
  mostly of process and tool documentation: how to run the verification
  after a code change, how to use GitHub, etc.

This commit is large, but text is mostly unchanged. A couple of
introductions and tables of content were added, but no significant
changes to the text have been made. These will be done in follow-ups.

Signed-off-by: Philipp Wagner <phw@lowrisc.org>
2020-09-28 22:30:00 +01:00