Greg Chadwick
bd248343cc
Enable the icache in coremark
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When executed on a configuration without an icache the enable is safe
but has no effect.
2024-02-05 21:02:42 +00:00
Greg Chadwick
63ac629d10
[coremark] Add option to coremark build to suppress pcount dump
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When using cosim checking performance counters won't match between ISS
and RTL. This option allows coremark to be run under cosim checking.
2021-11-12 09:39:38 +00:00
Canberk Topal
4b54d79fb4
[sw/fpga] coremark/link.ld update for FPGA sim
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This commit updates link.ld RAM length to include max BRAM capacity
for Arty A7-35. It also changes coremark makefile to include a .vmem
output, which then can be used for FPGA implementations.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
2021-08-03 16:51:16 +01:00
Greg Chadwick
adafa73ca8
[sw] Enable choice of -march= string for CoreMark
2020-07-10 13:49:19 +01:00
Pirmin Vogel
414ff7eeb0
[doc] Fix spelling of CoreMark
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Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2020-07-06 12:30:02 +02:00
Greg Chadwick
3927fd8d2a
[rtl/sw] Add multiply and divide wait counters
2020-03-13 14:48:29 +00:00
Greg Chadwick
6fc4110acf
[sw] Add Coremark makefile and support files
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Signed-off-by: Greg Chadwick <gac@lowrisc.org>
2020-03-09 14:41:40 +00:00
