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4 commits

Author SHA1 Message Date
Greg Chadwick
75e1c28107 [syn] Fix timing reports in synthesis flow
This fixes a bug where .csv.rpt files weren't being generated properly.
OpenSTA was outputting a simple 'Q' or 'D' for start and end path points
where the full instance name was required (which is then fed to yosys to
translate to a human readable name). The issue was in the `timing_report`
proc in syn/tcl/sta_utils.tcl which needed to request the full name of
the start and end points.

The syn README is updated to note which tool versions have been used to
test the flow.

Fixes #1193
2021-01-19 10:24:53 +00:00
Tom Roberts
35abca14ab [syn] Use latch-based register file in yosys
- Add a technology map for latches (only works with nandgate45 library
  at the moment)
- Add a real latch-based clock gating cell
- Update timing path reporting to differentiate between register and
  latch paths
- Update summary results in README to reflect the latch-based numbers,
  plus add numbers for a micro-riscy-style (RV32EC) config

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2020-08-10 13:36:32 +01:00
Greg Chadwick
2cfb5e8d78 [syn] Add STA util for investigating feedthroughs 2020-05-20 12:08:10 +01:00
Greg Chadwick
79bb6c7832 [syn] Synth flow improvements
Adds significant functionality to synthesis flow. Timing reports are
generated using OpenSTA and an area report is generated. Flow supports
open Nangate45 library from OpenROAD.
2020-01-07 14:09:17 +00:00