This commit creates a new top level wrapping the core, register file and
icache RAMs. The tracing top level is also renamed to ibex_top_tracing
to match. This new top level is intended to enable a dual core lockstep
implementation of Ibex.
There are no functional changes in this commit, only wiring.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This fixes a bug where .csv.rpt files weren't being generated properly.
OpenSTA was outputting a simple 'Q' or 'D' for start and end path points
where the full instance name was required (which is then fed to yosys to
translate to a human readable name). The issue was in the `timing_report`
proc in syn/tcl/sta_utils.tcl which needed to request the full name of
the start and end points.
The syn README is updated to note which tool versions have been used to
test the flow.
Fixes#1193
- Add a technology map for latches (only works with nandgate45 library
at the moment)
- Add a real latch-based clock gating cell
- Update timing path reporting to differentiate between register and
latch paths
- Update summary results in README to reflect the latch-based numbers,
plus add numbers for a micro-riscy-style (RV32EC) config
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
syn/ filling up with result directories is a little annoying, this sets
up the default so everything ends up generated under syn/syn_out/. Flow
users can easily change this to meet their personal requirements.
Adds significant functionality to synthesis flow. Timing reports are
generated using OpenSTA and an area report is generated. Flow supports
open Nangate45 library from OpenROAD.
