2 commits

Author	SHA1	Message	Date
Tom Roberts	35abca14ab	[syn] Use latch-based register file in yosys ... - Add a technology map for latches (only works with nandgate45 library at the moment) - Add a real latch-based clock gating cell - Update timing path reporting to differentiate between register and latch paths - Update summary results in README to reflect the latch-based numbers, plus add numbers for a micro-riscy-style (RV32EC) config Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>	2020-08-10 13:36:32 +01:00
Greg Chadwick	79bb6c7832	[syn] Synth flow improvements ... Adds significant functionality to synthesis flow. Timing reports are generated using OpenSTA and an area report is generated. Flow supports open Nangate45 library from OpenROAD.	2020-01-07 14:09:17 +00:00