7 commits

Author	SHA1	Message	Date
Marno van der Maas	2b1e3de746	Update lowrisc_ip to lowRISC/opentitan@0deeaa99e ... Update code from upstream repository https://github.com/lowRISC/opentitan to revision 0deeaa99e5760ee4f5c0a08e5fc1670509d22744 * [dv] Fix extension parsing in memutil (Gary Guo) * [dv,vcs] add an option to override debug_region vcs flag (Sharon Topaz) * [bazel,dvsim] fix airgapped cquery bug (Tim Trippel) * [prim_present/dv] Only test relevant configs and improve coverage (Michael Schaffner) * [prim_lfsr/dv] Add tests to improve coverage (Michael Schaffner) * [gpio/dv] Add second build mode for CDC prims (Michael Schaffner) * bugFix sim_cfg.hjson.tpl (skfwe wang) * [verilator] Add optional argument for trace file path (Alexander Williams) * [dv] Fix multibit bug in interrupt test register prediction (Michael Schaffner) * [dvsim] update sim.mk to accomodate OTP images under hw/ (Tim Trippel) * [doc] Remove defunct sectionContent macros (James Wainwright) * [util/uvmdvgen] Fix links in HW checklist template (Andreas Kurth) * [governance] Add `SEC_CM_SCOPED` to D1 Checklist (Andreas Kurth) * [dv/otp_ctrl] Fix cdc issue (Cindy Chen) * [dvsim] add custom wavefile option (Jaedon Kim) * [kmac,dv] fix regression - kmac_err (Jaedon Kim) * [dv/clk_rst_if] Avoid freeze due to rst undriven (Guillermo Maturana) * [top-level,clk_rst] Create separate clk_rst_if for xbar mode (Guillermo Maturana) * [chip,dv] update flash_wrtie mappping (Jaedon Kim) * [chip_tb] Integrate usbdpi into chip tb (Adrian Lees) * [dv/cdc] Enable CDC in four more IPs (Guillermo Maturana) * [dv/prim_alert] Enable CDC instrumentation (Guillermo Maturana) * [dv/prim] Enable CDC instrumentation for some prims (Guillermo Maturana) * [prim/rtl] Define `WITHIN_MARGIN` macro (Andreas Kurth) * Remove out-of-date "mode" in dvsim (Rupert Swarbrick) * [dv] Define `ASSERT_AT_RESET_AND_FINAL` macro (Andreas Kurth) * [dv] Define `ASSERT_AT_RESET` macro (Andreas Kurth) * [usb_diff_rx] Model pull-up behavior (Michael Schaffner) * [doc] Fix `that that` typo (Douglas Reis) * [doc] Fix `the the` typo (Douglas Reis) * [doc] Fixed broken file links (Hugo McNally) * [doc] Fixed links between books (Hugo McNally) * [doc] Fixed some broken links to external sites (Hugo McNally) * [doc] fixed links into github repos (Hugo McNally) * [doc] removed link to private repo (Hugo McNally) * [doc] Add DVSim design doc and glossary (Miguel Osorio) * [doc] Add new DVSim README (Miguel Osorio) * [doc] Move dvsim test planner into dvsim/doc (Miguel Osorio) * Add function called by dvsim publish to trigger a website rebuild (Harry Callahan) * [hw,dv_utils] Fix macro substitution issue with Xcelium (Raviteja Chatta) * [bazel,dvsim] enable passing `--data-perm` flag through dvsim/bazel (Timothy Trippel) * [doc] Updated documentation to reference the new build script. (Hugo McNally) * [doc] Update simulation results link (Raviteja Chatta) * [flash_ctrl] update `IPoly` parameter in flash scrambler (Timothy Trippel) * [dvsim] Removed depreciated Universal Newline flag (Hugo McNally) * [doc] Replace wavejson shortcodes with code-blocks (Hugo McNally) * [doc] Rewrite most frontmatters to Markdown titles (Hugo McNally) * [doc] Manually changed remaining hugo links (Hugo McNally) * [doc] Replaced Hugo links with standard markdown (Hugo McNally) * [doc] Created two initial mdbooks for new layout (Hugo McNally) * [doc mv] `util/` doc files moved for new layout. (Hugo McNally) * [doc mv] `hw/` doc files moved for new layout. (Hugo McNally) * [doc mv] hw/ip* doc files moved for new layout. (Hugo McNally) * [dv/verilator] Get '-c' flag of Verilator simulator working (Raphael Isemann) * [lint,prim_generic] Turn off unused Verilator lint in clock buf (Marno van der Maas) * [dv/util/sungrid] Fix issue when running sungrid in parallel (Eitan Shapira) * [dv/common] Fix xelium enum type issue (Cindy Chen) * [dvsim] Disable automatic timeout in gui mode (Cindy Chen) * [dvsim] Publish json results if available (Andreas Kurth) * [dvsim] Write json report to file (Andreas Kurth) * [dvsim] Generate json from run results (Andreas Kurth) * [dvsim] Add method to convert unit of JobTime (Andreas Kurth) * [dvsim] Add option to disable normalization of JobTime (Andreas Kurth) * [dvsim] Store coverage summary also in dict (Andreas Kurth) * [doc] Improve various titles (Marno van der Maas) * [doc] Added missing title headers (Marno van der Maas) * [doc] Add TODO to empty stubs (Marno van der Maas) * Add missing dependencies (Wojciech Sipak) * [dv] Add build options after file list (Sharon Topaz) * [rtl/prim] Fix prim_alert_receiver SVA for CDC (Guillermo Maturana) * [dv] Make prim_secded_* toggle coverage 100% (Weicai Yang) * [dv] Exclude prim_secdec_* in coverage collection (Weicai Yang) * [secded/fpv] Remove data input assumption (Michael Schaffner) * [fpv/prim_count] Add expected failure hjson (Cindy Chen) * [dv, rv_dm] Fix scoreboard (Srikrishna Iyer) * [dv, dv_macros] Expand DV_CLOCK_CONSTRAINT range (Srikrishna Iyer) * [dv, dv_base_reg] Add `get_mask_from_fields` function (Srikrishna Iyer) * [dv/xprop] Enable per-IP xprop configuration file (Guillermo Maturana) * [dv] Change alert_test to run with default build mode (Weicai Yang) * [dv,dvsim] Add run timeout multiplier option (Guillermo Maturana) * [dv/shadowed_reg] Reduce a env_cfg variable (Cindy Chen) * [dvsim] do not print status if `--interactive` (Eli Kim) * [dvsim] Add unlimited timeout (Eli Kim) * Revert "[dvsim] Add descriptions to timeout" (Eli Kim) * [dvsim] Fix flake8 lint error (Eli Kim) * [dvsim] Launch subprocess interactively (Eli Kim) * [dvsim] Add `--interactive` argument (Eli Kim) * [dvsim] Better dashboard result for parameterized blocks (Weicai Yang) * create the log in a correct way (Sharon Topaz) * Sungrid input from command file instead of command line (Sharon Topaz) * [chip dv] Fix compile time warnings - Xcelium (Srikrishna Iyer) * [dv] Clean up TODOs in csr_utils (Weicai Yang) * [dv] Clean TODOs in mem_bkdr_* (Weicai Yang) * [chip dv] Fix compile warnings in RTL and DV (Srikrishna Iyer) * [dv] Resolve/clean up more TODOs (Weicai Yang) * [dvsim] Add descriptions to timeout (Eli Kim) * [fpv] Clean up strong property in simulation (Cindy Chen) * [dv/xprop] Change code to be more xprop-friendly (Guillermo Maturana) * [dv] Clean up TODOs in dv_lib (Weicai Yang) * [chip dv] Implement the E2E JTAG debug and inject tests (Srikrishna Iyer) * [dv, util] Add read_vmem function (Srikrishna Iyer) * [dv str_utils_pkg] Add more string util methods (Srikrishna Iyer) * [dv] Move sw_symbol_get_addr_size to dv_utils_pkg (Srikrishna Iyer) * [dv, sim.mk] Copy elf file without .bin suffix (Srikrishna Iyer) * [dv] Resolve TODOs in cip_macros (Weicai Yang) * [prim_sparse_fsm_flop] Make DV statement x-prop safe (Michael Schaffner) * [dv/cov] Exclude coverage of dv-only code (Guillermo Maturana) * [dv/chip] Disable alert ping scb default check (Cindy Chen) * [dv] ensure RAM ELF file gets copied to the rundir (Timothy Trippel) * [dv] Use build seed to regenerate LC encoding for each build (Michael Schaffner) * [dv/coverage_cfg] Remove coverage of prim_onehot_check (Guillermo Maturana) * [prim] Add sync_req_ack based async FIFO (Michael Schaffner) * [prim] Add RZ protocol to prim_sync_reqack* (Michael Schaffner) * [dvsim] Move empty pattern list to common (Eli Kim) * [prim] Reset assertion improvement (Canberk Topal) * [prim_mubi*_sync] Remove explicit mux prim to improve coverage (Michael Schaffner) * [fpv] Support build_pass_pattern in OneShotCfg (Cindy Chen) * [dv] Increase MAX_CYCLE to 30 in sec_cm SVA (Weicai Yang) * [dv_macros] Kill live assertions when disabling in `DV_ASSERT_CTRL` (Andreas Kurth) * [dv, csr_utils_pkg] Add user frontdoor mechanism on all CSR methods (Srikrishna Iyer) * [dv/chip] Support exclude certain alert injections in all_escalation test (Cindy Chen) * [dv, csr_utils_pkg] Fix csr_read for field accesses (Srikrishna Iyer) * [prim-cdc-rand-delay] Fix bug due to dv macro (Srikrishna Iyer) * [verilator] Simulate GPIOs with weak pull up/down. (Chris Frantz) * [dv,bazel] only copy over an ELF file if one exists (Timothy Trippel) * [chip,dv,i2c] en_monitor update for top_earlgrey (Jaedon Kim) Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>	2023-07-06 07:55:47 +00:00
Marno van der Maas	90a81a3cc7	Update lowrisc_ip to lowRISC/opentitan@f9e667550 ... Update code from upstream repository https://github.com/lowRISC/opentitan to revision f9e6675507fdd81e0b0dd3481c0a4bca634f322d * [ralgen] Minor correction in alias-file passing mechanism (Michael Schaffner) * [entropy_src/dv] Track FW_OV FIFO exceptions (Martin Lueker-Boden) * [dv/clkmgr] Fix reset handling (Guillermo Maturana) * [flash_ctrl] Add generic registers for the flash wrapper (Michael Schaffner) * [fpv/prim_onehot_check] Fix prim_onehot_check compile error (Cindy Chen) * [dvsim] Minor cleanup of job_runtime updates (Srikrishna Iyer) * [chip/dv] replace wait with DV_WAIT (Weicai Yang) * [dv] Add DV_WAIT macro (Weicai Yang) * [dvsim] Display max CPU time in regression result (Cindy Chen) * [dv, xcelium] Indicate SVA-disabled hierarchies (Srikrishna Iyer) * [dv, xcelium] Update switches, sim finishi (Srikrishna Iyer) * [utils,dvsim] Add wall-clock timeout feature (Guillermo Maturana) * [prim_count] This reworks the primitive to make it more generic (Michael Schaffner) * [dvsim] remove unecessary `sw_build_dir` parameter (Timothy Trippel) * [dvsim] use Bazel labels for SW images (Timothy Trippel) * [entropy_src/dv] Refactor entropy_src_rng_vseq (Martin Lueker-Boden) * [dv, waves] Improve wave dumping (Srikrishna Iyer) * [dv/kmac] Fix EDN timeout assertion failures (Cindy Chen) * [doc] Move style guides into a separate section (Miguel Osorio) * [spi_device/dv] Enable testing SFDP command (Weicai Yang) * [doc] Unlist dangling pages from menus. (Miguel Osorio) * [doc] Add DV intermediate sections (Miguel Osorio) * [doc] Skip markdown templates from the build (Miguel Osorio) * [dv/verilator] Fix numeric base of simulation statistics (Andreas Kurth) * [dvsim] Make email.html filename more descriptive (Srikrishna Iyer) * [csrng/dv] Add deposit to force states when disabled (Steve Nelson) * fix(rdc): typo (Eunchan Kim) * fix(rdc): Include NEW violations only to report (Eunchan Kim) * [dvsim] Add support for SW (bazel) build opts (Srikrishna Iyer) * fix(cdc): Parse NEW violations only (Eunchan Kim) * feat(rdc): Add Meridian RDC log parser (Eunchan Kim) * feat(rdc): Add Meridian RDC flow to dvsim (Eunchan Kim) * [dv/cip_base] Add checking in stress_all_with_rand_reset seq (Cindy Chen) * [clkmgr/prim] Make frequency measurement disable more robust (Timothy Chen) * [prim/lint] Update waivers (Michael Schaffner) * [doc] Update D2 checklist (Michael Schaffner) * [clang-format] Format all covered files (Alexander Williams) * [dvsim] Indicate what is currently running (Srikrishna Iyer) * [doc] Fix trailing whitespace on md files. (Miguel Osorio) * [doc] Remove README.md files from hw,utils folders (Miguel Osorio) * [tools/dv] Modify common.ccf file for proper expression coverage (Steve Nelson) * [prim_edn_req] Accumulate repetition errors until the data is consumed (Pirmin Vogel) * [chip dv] Cleanup task invoked in func warning (Srikrishna Iyer) * [topgen] Pass alias register paths into topgen for top RAL generation (Michael Schaffner) * [dv] Split debug_access opt to another hjson variable for override (Weicai Yang) * [dv] Fix ping exclusion (Weicai Yang) * [prim] update register CDC scheme (Timothy Chen) * [dv] Add assertion to check reg_we onehot error leads to a fatal alert (Weicai Yang) * [sw,tests] Test flash_ctrl init and scramble (Dave Williams) * [PRIM] new clock mux to prevent a glitch (Joshua Park) * [dv] Add prim_cdc_rand_delay exclusion in cover_reg_top (Weicai Yang) * [prim] Add additional qualification to the trigger (Timothy Chen) * [prim] Add description to parameters (Timothy Chen) * [sw,tests] Add -f option to copy in sim.mk (Dave Williams) * [top/spi_device] constraint and clock updates (Timothy Chen) * [dv] Update xcelium coverage config file (Weicai Yang) * fix(prim): High memory usage of Assertion (Eunchan Kim) * [top,dv] rv_dm agent update (Jaedon Kim) * [dv] Enable reg_wr_check test for all blocks (Weicai Yang) * [dv] Update tl testplan for reg write enable check (Weicai Yang) * Refixed 12236 to a more rubust solution (Rasmus Madsen) * [fpv/alert_handler] Add sec_cm FPV testbench for alert_handler (Cindy Chen) * [dv,ralgen] revert `ralgen.py` to use relative file paths (Timothy Trippel) * [dv,ralgen] update `ralgen.py` to use git paths over relative (Timothy Trippel) * doc(prim): Specify ICEBOX for prim_packer (Eunchan Kim) * [bazel,dvsim] update dvsim.py to use Bazel to build SW (Timothy Trippel) * [prim] Added generic xnor2 (Arnon Sharlin) * [flash_ctrl/prim_flash] Add parameters to tweak module latency (Timothy Chen) * [prim_assert] Fix ASSERT_FPV_LINEAR_FSM (Guillermo Maturana) * [chip,rstmgr,dv] regression fix rstmgr_alert_info test (Jaedon Kim) * [dv/tool] Collect csr assertion cov (Cindy Chen) * [otp_ctrl] Add generic registers for prim_otp_wrapper (Michael Schaffner) * [dvsim] Use leaf most field if conflict rather than Exception (Eunchan Kim) * [regtool] Extend UVM backend to support alias definitions (Michael Schaffner) * [fvp/pwrmgr] Pwrmgr fsm error (Cindy Chen) * [dvsim] Revert lowRISC/opentitan#12761 to build SW with meson (Timothy Trippel) * [bazel,dvsim] update dvsim.py to use Bazel to build SW (Timothy Trippel) * [prim] removed unused files (Timothy Chen) * [flash_ctrl] Harden FIFO pointers (Timothy Chen) * [dv] Remove TB_LINT_PASS in all IP checklists (Weicai Yang) * [dv/flash_ctrl] Temp fix flash_ctrl regression compile error (Cindy Chen) * fix(prim): Lint fix for line length (Eunchan Kim) * fix(prim): Lint warning for `err_o` (Eunchan Kim) * [dv] Fix Xcelium toggle collection (Weicai Yang) * [hw/ip] Add extra prim_fifo_sync port (Timothy Chen) * [prim/fifo] Add option to harden prim fifo pointers (Timothy Chen) * [dv_base_reg] Extend search by name functions (Michael Schaffner) * [fpv/lc_ctrl] Add gating conditions for sec_cm assertions (Cindy Chen) * [primgen] Sort the parameters (Weicai Yang) * [python] flake8 lint cleanups (Michael Schaffner) * [prim_subreg] Remove anchor bufs since they are not needed (Michael Schaffner) * [dv] Add `-xprop=mmsopt` run-opt for VCS (Weicai Yang) * [dv] Temporarily remove CDC assertions (Weicai Yang) * [hw/dv] further updated dv flow to now score systemverilog tasks and functions (Rasmus Madsen) * [dv/chip] Fix bit_bash timeout error (Cindy Chen) * [flash_ctrl] Allow fixed priority arbiter (Timothy Chen) * [prim_assert] Minor rewording in comment (Michael Schaffner) * [dv/xcelium] 1 attempt of cleaning up the coverage files (Rasmus Madsen) * [dvsim] revert lowRISC/opentitan#12319 to fix CI (Timothy Trippel) * [primgen] Sort the parameters to ensure stable order (Weicai Yang) * [prim] Fix python style (Weicai Yang) * [bazel] update dvsim.py to build ROMs with bazel (Timothy Trippel) * [dvsim] Correct argparse usage statement and help (Drew Macrae) * [prim_assert] Fix assertion include order (Michael Schaffner) * [ast] Lint fixes and waiver updates (Michael Schaffner) * [prim/lc_ctrl] Create a common assertion macro for linear FSM check (Michael Schaffner) * [dv/csr_utils] Clean up mem_rd/wr print out message (Cindy Chen) * [doc] Update D3 checklist per RFC (Michael Schaffner) * [prim_dom_and_2share] Allow re-use of intermediate results for remasking (Pirmin Vogel) * [prim_dom_and_2share] Add parameter to enable full/optional pipelining (Pirmin Vogel) * [dv/vcs] Update cdc exclusion keyword (Cindy Chen) * [prim] Add a duplicated prim_arbiter instance (Timothy Chen) * [dv/cdc assertion] Temp remove CDC assertion cov collection in VCS (Cindy Chen) * [prim_onehot_check] Rework lint fix (Michael Schaffner) * [mubi/lc_ctrl] Change MUBI / lc_tx_t encodings (Michael Schaffner) * [dv] Update xcelium cover.ccf to only enable coverage for dut (Weicai Yang) * [dv/xcelium] Fix Xcelium nightly regression error (Cindy Chen) * [prim_onehot_mux] Add lint waivers (Michael Schaffner) * [prim_lc_sender] Add waiver (Michael Schaffner) * [prim_mubi] Make sure waiver file is listed in core file (Michael Schaffner) * [tlul_fifo_async] Move waiver to correct file and remove old waivers (Michael Schaffner) * [prim_blanker] Remove prim_and2 waiver file (Michael Schaffner) * [prim_packer] Lint fixes (Michael Schaffner) * [prim_secded] Add lint waiver file (Michael Schaffner) * [dv/cov] Exclude CDC module from collecting coverage (Cindy Chen) * [reggen] Add spurious WE check to autogen'd regfile (Michael Schaffner) * [prim_reg_we_check] Add spurious CSR write checker (Michael Schaffner) * [prim_onehot_check] Add option for permissive en_i checks (Michael Schaffner) * [tools/dv] updated UNR flow to support xcelium/jg (Rasmus Madsen) * [prim] Add dv_macros missing dependency (Timothy Chen) * [top, dv] Fix ext clk plusarg (Weicai Yang) * [dv/build_seed] Fix build_seed (Cindy Chen) * [clkmgr] Correct the disable condition (Timothy Chen) * [flash, dv] Fix RMA test backdoor symbol overwrite (Weicai Yang) * [top, dv] Fix rom backdoor symbol overwrite (Weicai Yang) * [flash_ctrl] Add checks for unexpected acks (Timothy Chen) * [prim_present] Add Verilator lint waiver (Michael Schaffner) * [xcelium] Pass cov_merge_db_dir through to cov_report.tcl (Rupert Swarbrick) * [dv/build_seed] Fix build seed errors (Cindy Chen) * [prim_mubi] Add assertion to check that the values are complementary (Michael Schaffner) Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>	2022-08-05 18:00:25 +01:00
Canberk Topal	53b1732b19	Update lowrisc_ip to lowRISC/opentitan@3a672eb36 ... This commit also adds memory manipulation package in ibex repository. Update code from upstream repository https://github.com/lowRISC/opentitan to revision 3a672eb36aee5942d0912a15d15055b1d21c33d6 * [mubi] Fix path in auto-gen header (Rupert Swarbrick) * [dv] Allow using memutil_dpi_scrambled even without prim_ram_1p_scr (Rupert Swarbrick) * [prim] Fix prim_ram_1p_scr Dependencies (Canberk Topal) * [dv/clk_rst_if] Split clk_rst_if jitter to 2 different values (Eitan Shapira) * [dv] Add external hjson path support in ralgen (Srikrishna Iyer) * [dv] Add sub RAL block creation knobs (Srikrishna Iyer) * [pwrmgr] Make rom_ctrl check signals multi-bit (Timothy Chen) * [dv/alert_handler] Randomize mubi input (Cindy Chen) * [flash_ctrl] Fix bank erase / info partition issue (Timothy Chen) * [ci] Fix CI failure (Weicai Yang) * [Cleanup] Remove lc_tx_e type and replace it with lc_tx_t (Weicai Yang) * [aes] Add gtech synthesis setup (Michael Schaffner) * [mubi] Enhance mubi_sync with stability check (Timothy Chen) * [prim] Fix prim_packer_fifo when ClearOnRead is false (Rupert Swarbrick) * [cleanup] Remove mubi4_e and replace it with mubi4_t (Weicai Yang) * [dv] Fix shape calculations for replicated ECC (Rupert Swarbrick) * [dv/alert] Support LPG in alert_sender/receiver pair (Cindy Chen) * [dv] Add a ReadWithIntegrity method to Ecc32MemArea (Rupert Swarbrick) * [dv] Simplify Ecc32MemArea read/write functions (Rupert Swarbrick) * [prim] Add option to not clear the packer FIFO upon read (Pirmin Vogel) * [dv] Change intg_err test from V3 to V2S (Weicai Yang) * [util] Delete generate_prim_mubi.py (Rupert Swarbrick) * [dv] Slightly generalise run_stress_all_with_rand_reset_vseq (Rupert Swarbrick) * [fpv] Fix some assumptions in prim_count (Cindy Chen) * [prim] quick path to prim_count assertion (Timothy Chen) * [dv] Support Multiple EDN Interfaces in OpenTitan (Canberk Topal) * [prim] Add xoshiro256pp primitive. (Vladimir Rozic) * [dv/prim_alert] Fix async fatal alert regression error (Cindy Chen) * [prim] Add missing include to prim_xilinx_pad_wrapper (Rupert Swarbrick) * [prim] Add missing include to prim_mubi_dec* (Rupert Swarbrick) * [dv/prim_alert_receiver] Fix assertion that consumes large mem (Cindy Chen) * [prim] Remove extra semicolon (Weicai Yang) * [chip,dv] Refactor CSR exclusion method (Srikrishna Iyer) * [top, all] update connects for mubi (Timothy Chen) * [flash_ctrl] Add plain text integrity in flash (Timothy Chen) * [prim] Add time-out functionality to prim_clock_meas (Timothy Chen) * [prim] Fix DC sythesis error (Weicai Yang) * [fpv] Fix regression failures (Cindy Chen) * [dv/ralgen] Update `dv_base_names` input from a string to a list (Cindy Chen) * [dv/ralgen] Update the `dv-base-prefix` optional input (Cindy Chen) * [doc] Add D2S and V2S checklist items to all checklists (Michael Schaffner) * [dv] Test security countermeasures (Weicai Yang) * [dv] Fix ASSERT_INIT race condition (Weicai Yang) * [syn/aes/otbn] Minor fixes to fix block level synthesis (Michael Schaffner) * [all] updated assert rtl ifdef (Timothy Chen) * [dv] Update TL intg testplan (Weicai Yang) * [prim] Add prim_fifo_async_sram_adapter to FPV list (Eunchan Kim) * [spi_device] Upload Cmd/Addr FIFO status revision (Eunchan Kim) * [dvsim] Modify resolve_branch to handle branch names with forward slash. (Todd Broch) * [prim_clock_inv] Add option to disable FPGA BUFG (Michael Schaffner) * [ralgen] Be more explicit which tool is called (Philipp Wagner) * [prim] Tweak prim_sync_reqack_data assertion so it can be disabled (Rupert Swarbrick) * [verible] Rename rule file (Philipp Wagner) * [dv/base_monitor] Cleaned up base monitor (Rasmus Madsen) * [fpv] prim_counter_fpv (Cindy Chen) * [dv/shadow_reg] Cross shadow reg error sequence with csr rw (Cindy Chen) * [dv] Fix scb multi-ral (Weicai Yang) * [dvsim] Enabling glob-style patterns for -i switch (Srikrishna Iyer) * [dv] Split sec_cm_testplan into multiple testplans (Weicai Yang) * [dv/dsim] Remove dsim's system_lib from library path (Guillermo Maturana) * [prim_packer] Resolve width mismatch (Philipp Wagner) * [prim] Fix lint error in prim_util_memload (Philipp Wagner) * [prim] Minor fix to make conn checks easy (Srikrishna Iyer) * [fpv] prim_secded FPV testbench updates bind file naming (Cindy Chen) * [dv_macros.svh] minor cleanup (Srikrishna Iyer) * [dv,xcelium] minor cleanup (Srikrishna Iyer) * [dv/shadowed_reset] Add a shadowed_rst_n interface (Cindy Chen) * [fpv] Update FPV file naming (Cindy Chen) * [top] Convert to mubi usage in some areas (Timothy Chen) * [entropy_src] mubi updates (Timothy Chen) * [prim] Add test for mubi invalid (Timothy Chen) * [prim_double_lfsr] Add duplicated LFSR primitive (Michael Schaffner) * [dv] Fix shadow reg backdoor path and enable csr_reset sequence (Weicai Yang) * [prim] Fix unused net (Timothy Chen) * [dv, clk_rst_if] Improve jitter and add scaling (Srikrishna Iyer) * [prim] Anchor buffers around register flip flops (Timothy Chen) * [alert_handler/top] Lint fixes and lc_tx_t to mubi4_t conversions (Michael Schaffner) * [prim_mubi] Replace true/false_value() functions with parameter (Michael Schaffner) * [dv/dsim] Get dsim to work at full chip (Guillermo Maturana) * [prim] Fixes for prim_count (Timothy Chen) * [top] Add various anchor points to modules (Timothy Chen) * [dv/pwrmgr] Add wakeup test sequence (Guillermo Maturana) * [reggen] Add mubi support into hjson (Timothy Chen) * [dv/shadow_reg] Fix aes shadow reg failure (Cindy Chen) * [dv/cdc] CDC simulation model (Udi Jonnalagadda) * [prim_lfsr/lint] Add temporary waiver for LOOP_VAR_OP lint error (Michael Schaffner) * [prim_clock_buf] Add lint waiver for unused parameter (Michael Schaffner) * [dvsim] Correctly set self_dir for included Hjson files (Philipp Wagner) * [util] Add tooling support for V2S milestone (Srikrishna Iyer) * [prim_mubi] Add decoder module similar to prim_lc_dec (Michael Schaffner) * [prim_mubi] Add mubi sender and sync primitives (Michael Schaffner) * [prim_mubi_pkg] Switch to True/False terminology (Michael Schaffner) * [prim] Minor work-around for xcelium (Timothy Chen) Signed-off-by: Canberk Topal <ctopal@lowrisc.org>	2021-11-29 17:25:30 +00:00
Rupert Swarbrick	7d61def943	Update lowrisc_ip to lowRISC/opentitan@f29a0f7a7 ... Update code from upstream repository https://github.com/lowRISC/opentitan to revision f29a0f7a7115e03fba734b1c00691c253aceb07e. The list of OpenTitan changes that are merged in appears at the bottom of the commit. There are some manual changes needed to adapt the code to work with these changes. - The ICache monitors need some extra types to adapt to the (rather odd) data model that the OpenTitan dv_lib code now uses, where a monitor needs to know an agent's associated sequence type. - Verilator simulations now use MemArea slightly differently OpenTitan changes: * [dv] Allow monitor items to have different types from sequence items (Rupert Swarbrick) * [dvsim] Fix primary_cfg handling (Srikrishna Iyer) * [dvsim] Deal with non unicode chars in log files (Srikrishna Iyer) * [dvsim] Added common build fail patterns (Srikrishna Iyer) * [dvsim] Minot cleanup to the lint flow (Srikrishna Iyer) * [dvsim] Minor cleanups to to formal flow (Srikrishna Iyer) * [dvsim] Fixes to UNR and cov analysis flows (Srikrishna Iyer) * [dvsim] Very minor cleanup of Deploy class (Srikrishna Iyer) * [dvsim] LsfLauncher report early errors as F (Srikrishna Iyer) * [dvsim] Minor fix in clean_odirs function (Srikrishna Iyer) * [chip dv] Set +sw_images as comma-separated list (Srikrishna Iyer) * [flash_ctrl] Split tl intefaces for flash_ctrl and prim_flash_cfg (Timothy Chen) * [keymgr] Fix input value checks (Timothy Chen) * [formal/script] Update generic formal flow naming from `fpv` to `formal` (Cindy Chen) * [top, prim] Address wmask and data width mismatch issue (Timothy Chen) * [dvsim] Add GUI mode for running simulations (Srikrishna Iyer) * [dv] Fix reg backdoor (Weicai Yang) * [dpi] Make an "ECC32" flavour of MemArea (Rupert Swarbrick) * [uvmdvgen] Fix has_interrupts in env_cfg (Cindy Chen) * [dvsim] Keep dependencies list (Srikrishna Iyer) * [prim_prince] Reverse the k0||k1 mapping to match with the paper (Michael Schaffner) * [dvsim] Fix printing of last 10 lines (Srikrishna Iyer) * [primgen] Minor fix to enable types with underscores (Michael Schaffner) * [dvsim] Prevent command echo suppression (Srikrishna Iyer) * [dvsim] Spot fixes for LSF and internal launcher (Srikrishna Iyer) * [sva] csr assertion dependency update (Cindy Chen) * [memutil] Change DpiMemUtil so that it no longer owns MemAreas (Rupert Swarbrick) * [memutil] Factor out MemArea as a class (Rupert Swarbrick) * [prim] Split out PRESENT and PRINCE support from prim:all (Rupert Swarbrick) * [fpv/otp_ctrl] Disable assertions due to lc_esc_en (Cindy Chen) * [prim_prince] Annotate some arrays to avoid UNOPTFLAT warnings (Rupert Swarbrick) * [top] Hook up latest ast ports and complete a few other integration (Timothy Chen) * Eliminate `#pragma once` in favor of include guards (Chris Frantz) * [sw,dv] Update headers to pass fix_include_guards.py (Alex Bradbury) * [xbar/dv] Fix assertion error due to short reset (Weicai Yang) * [sram] Add memory initialization (Timothy Chen) * [uvmdvgen] Update links in checklist template (Philipp Wagner) * [dv/uvmdvgen] Add comment for testplan (Cindy Chen) * [dv/top_earlgrey] chip csr_aliasing timeout (Cindy Chen) * [dvsim] Cosmetic updates to launcher methods (Srikrishna Iyer) * [dv] Update csr_wr to support field write (Weicai Yang) * [dv/common] Fix regression warnings (Cindy Chen) * [dv] Get blocks with multiple device interfaces working with chip DV (Rupert Swarbrick) * [doc] Use relative links in Hjson-related shortcodes (Philipp Wagner) * [dvsim] minor enhancement to clean_odir (Srikrishna Iyer) * [dvsim] Statically display jobs' status (Srikrishna Iyer) * [dvsim] Do weighted scheduling of jobs (Srikrishna Iyer) * [dvsim] Schedule jobs by dependency (Srikrishna Iyer) * [dv] Xcelium UNR typo (Srikrishna Iyer) * [dvsim] Implement LsfLauncher (Srikrishna Iyer) * [dv/chip] solve same_csr_outstanding_timeout (Cindy Chen) * [dv] make dv_base_agent work for high-level agent (Weicai Yang) * [tools/dv] added UNR flow for xcelium (Rasmus Madsen) * [prim] Split prim:subreg out of prim:all (Rupert Swarbrick) * [prim] Split prim_alert_* out of prim:all (Rupert Swarbrick) * [prim] Split out fifos into a prim_fifo core (Rupert Swarbrick) * [prim] Split out arbiters into a prim_arbiter core (Rupert Swarbrick) * [prim] Make prim:flop_2sync depend on prim:flop (Rupert Swarbrick) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>	2021-04-06 12:49:51 +01:00
Greg Chadwick	d717e2385e	Update lowrisc_ip to lowRISC/opentitan@7aa5c2b89 ... Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7aa5c2b890fa5d4e3d0b43e0f5e561cb7743a01d * [flash] updated flash wrapper md file (Dana Agur) * [flash / top / ast] functional updates (Timothy Chen) * [ralgen, dv] Associated changes to ralgen (Srikrishna Iyer) * [prim_sync_reqack_data] Fix SVA checking DST-to-SRC data stability (Pirmin Vogel) * [dv/keymgr] temp disable alert checking in scb (Cindy Chen) * [dvsim] Fix a wrong path in print message (Weicai Yang) * [prim] Teach verilator to recognise a clock gate (Rupert Swarbrick) * [prim_lc_sync] Add AsyncOn parameter to enable/disable the sync flops (Michael Schaffner) * [clkmgr / top] Add clock divider step down to support lc_ctrl transition (Timothy Chen) * [prim_sync_reqack] Use NRZ protocol internally for increased throughput (Pirmin Vogel) * [prim] correct interface documentation. (Timothy Chen) * [flash_ctrl] Add tlul configuration interface to prim_flash (Timothy Chen) * [flash_ctrl] Use hamming code for 64b ECC (Timothy Chen) * [prim/edn] Fix lint error (width mismatch) (Eunchan Kim) Signed-off-by: Greg Chadwick <gac@lowrisc.org>	2021-01-22 11:12:08 +00:00
Philipp Wagner	b1daf9e44e	Update lowrisc_ip to lowRISC/opentitan@c277e3a8 ... Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7e131447da6d5f3044666a17974e15df44f0328b Updates to Ibex code to match this import: * Include str_utils in the imported code. * List new source files in dv/uvm/core_ibex/ibex_dv.f * Update patches to resolve merge conflicts. * Update tb_cs_registers.cc and ibex_riscv_compliance.cc to match the new return code of simctrl.Exec(). Imported updates: * Do not require pyyaml >= 5.1 (Philipp Wagner) * [prim_edn_req] Forward fips signal to consumer (Pirmin Vogel) * [prim_edn_req] Use prim_sync_reqack_data primitive (Pirmin Vogel) * [prim_edn_req] De-assert EDN request if packer FIFO has data available (Pirmin Vogel) * [cleanup] Mass replace tabs with spaces (Srikrishna Iyer) * [lc_ctrl] Add script to generate the LC state based on the ECC poly (Michael Schaffner) * [dvsim] Use list for rsync command (Eunchan Kim) * [verilator] Only control the reset line when necessary (Rupert Swarbrick) * [dv/csr_utils] Add debug msg for UVM_NOT_OK err (Cindy Chen) * [dvsim] Add exclude hidden files when needed (Eunchan Kim) * [prim_sync_reqack] Add variant with associated data and optional data reg (Pirmin Vogel) * [DV, Xcelium] Fix for lowRISC/opentitan#4690 (Srikrishna Iyer) * [dvsim] Remote copy update (Srikrishna Iyer) * [prim_edn_req] Add EDN sync and packer gadget primitive (Michael Schaffner) * [prim] Add hamming code as ECC option (Timothy Chen) * [DV] Cleanup lint warnings with Verible lint (¨Srikrishna) * [prim_ram] Rearrange parity bit packing and fix wrong wmask settings (Michael Schaffner) * [lc_sync/lc_sender] Absorb flops within lc_sender (Michael Schaffner) * [prim_otp_pkg] Move prim interface constants into separate package (Michael Schaffner) * [sram_ctrl] Pull scr macro out of sram_ctrl (Michael Schaffner) * [top] Move alert handler to periphs and attach escalation clock to ibex (Michael Schaffner) * [prim_esc_rxtx/rv_core_ibex] Add default values and NMI synchronization (Michael Schaffner) * [dvsim] Fix regression publish result link with --remote switch (Cindy Chen) * [vendor/ibex] Remove duplicate check tool requirements files (Michael Schaffner) * [prim_ram_1p_scr] Fix sequencing bug in scrambling logic (Michael Schaffner) * [prim_ram*_adv] Qualify error output signals with rvalid (Michael Schaffner) * [dvsim] Fix purge not delete remote repo_top (Cindy Chen) * [lc/otp/alerts] Place size-only buffers on all multibit signals (Michael Schaffner) * [prim_buf] Add generic and Xilinx buffer primitive (Michael Schaffner) * [prim] Packer to add byte hint assertion (Eunchan Kim) * [dvsim] Logic to copy repo to scratch area (Srikrishna Iyer) * [dv/lc_ctrl] enable lc_ctrl alert_test (Cindy Chen) * [prim] documentation update for flash (Timothy Chen) * [flash_ctrl] Add additional interface support (Timothy Chen) * [dvsim] Fix publish report path (Weicai Yang) * [top_earlgrey] Instantiate LC controller in toplevel (Michael Schaffner) * [doc] Fix checklist items in V1 (Michael Schaffner) * [dv/csr_excl] Fix VCS warning (Cindy Chen) * [dv/doc] cleaned up checkist alignment (Rasmus Madsen) * [doc/dv] cleanup (Rasmus Madsen) * [dv/doc] updated dv_plan links to new location (Rasmus Madsen) * [dv/doc] changed testplan to dv_plan in markdown files (Rasmus Madsen) * [dv/doc] changed dv plan to dv doc (Rasmus Madsen) * Remove redundant ascentlint options (Olof Kindgren) * Add ascentlint default options for all cores depending on lint:common (Olof Kindgren) * [flash] documentation update (Timothy Chen) * [flash / top] Add info_sel to flash interface (Timothy Chen) * [otp] lci interface assertion related fix (Cindy Chen) * [dv/uvmdvgen] Add switch to auto-gen edn (Cindy Chen) * [util] Rejig how we load hjson configurations for dvsim.py (Rupert Swarbrick) * added changes required by sriyerg (Dawid Zimonczyk) * update riviera.hjson (Dawid Zimonczyk) * [flash_ctrl] Add high endurance region attribute (Timothy Chen) * Change VerilatorSimCtrl::Exec to handle --help properly (Rupert Swarbrick) * Simplify handling of exit_app in VerilatorSimCtrl::ParseCommandArgs (Rupert Swarbrick) * [sram_ctrl] Rtl lint fix (Michael Schaffner) * [keymgr] Add edn support (Timothy Chen) * [dv] Make width conversion explicit in dv_base_env_cfg::initialize (Rupert Swarbrick) * [dvsim] Allow dvsim.py to be run under Make (Rupert Swarbrick) * [dvsim[ rename revision_string to revision (Srikrishna Iyer) * [dvsim] Update log messages (Srikrishna Iyer) * [dvsim] fix for full verbosity (Srikrishna Iyer) * [dv] Fix Questa warning and remove unused var (Weicai Yang) * [dvsim] Add alias for --run-only (Weicai Yang) * [keymgr] Hook-up random compile time constants (Timothy Chen) * [dvsim] Add support for UVM_FULL over cmd line (Srikrishna Iyer) * [dv common] Enable DV macros in non-UVM components (Srikrishna Iyer) * [DVsim] Add support for Verilator (Srikrishna Iyer) * [DVSim] Fix how sw_images is treated (Srikrishna Iyer) * [DV common] Fixes in sim.mk for Verilator (Srikrishna Iyer) * [DV Common] Split DV test status reporting logic (Srikrishna Iyer) * [prim_arbiter_ppc] Fix lint error (Philipp Wagner) * [DV common] Factor `sim_tops` out of build_opts (Srikrishna Iyer) * [dvsim] run yapf to fix style (Weicai Yang) * [dv/common] VCS UNR flow (Weicai Yang) * [dv] Add get_max_offset function in dv_base_reg_block (Weicai Yang) * [otp_ctrl] Fix warnings from VCS (Cindy Chen) * [lint] Change unused_ waiver (Eunchan Kim) * [dv/alert_test] Add alert_test IP level automation test (Cindy Chen) * [DV] Update the was SW is built for DV (Srikrishna Iyer) * [dvsim] Replace `sw_test` with `sw_images` (Srikrishna Iyer) * [chip dv] Move sw build directory (Srikrishna Iyer) * [dv common] Update dv_utils to use str_utils_pkg (Srikrishna Iyer) * [DVSim] Method to add pre/post build/run steps (Srikrishna Iyer) Signed-off-by: Philipp Wagner <phw@lowrisc.org>	2021-01-07 18:03:44 +00:00
Rupert Swarbrick	623402cf6f	Vendor in hw/dv/{data,tools} from OpenTitan ... This gets the rest of the support code needed for dvsim (which we currently duplicate). The patch: - adds the relevant directories to the vendoring file - adds a patch to rewrite some OpenTitan-specific bits - adds a "common_project_cfg.hjson" - re-runs the vendoring tool This patch won't yet change how DV code runs; we also need to redirect a couple of paths and delete dv/uvm/data for that. This will happen in the next patch. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>	2020-11-28 12:12:27 +00:00