Commit graph

4 commits

Author SHA1 Message Date
Rupert Swarbrick
9f14922382 [dv] Construct ISA string from RTL parameters for cosim tests 2022-02-17 16:06:53 +00:00
Pirmin Vogel
9559bbb6ff Add RegFile parameter for selecting register file implementation
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2020-08-21 14:20:34 +02:00
Pirmin Vogel
2ef5e5e3f2 Add a single RV32M enum parameter to select multiplier implementation
This commit replaces the previous combination of `RV32M` bit parameter
used to en/disable the M extension and the `MultiplierImplementation`
used to select the multiplier implementation by a single enum parameter.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2020-08-20 11:50:08 +02:00
Rupert Swarbrick
210634586d Fix last verilator warning for ibex_simple_system; add waiver
If you just build simple_system a fusesoc line like

  fusesoc --cores-root=. run --target=sim --setup \
          --build lowrisc:ibex:ibex_simple_system

then the change to ibex_simple_system.sv suffices, but if you
explicitly set a parameter in fusesoc like this:

  fusesoc --cores-root=. run --target=sim --setup \
          --build lowrisc:ibex:ibex_simple_system \
		  --RV32M=1

then it overrides the default parameter with a literal 1. We declare
the parameter as an 'int', so I guess that's quite a reasonable
behaviour from fusesoc. Anyway, this check only triggers when a 1-bit
parameter is set with a literal 1, so should be safe. (If you do
something buggy like setting it to 2, it will still moan at you). This
patch adds a waiver file in examples/simple_system that silences the
warning.

This patch also makes the equivalent change to riscv_compliance,
adding a waiver file in dv/riscv_compliance/lint and fixing up the
default parameters.
2020-03-03 11:35:07 +00:00