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96 lines
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96 lines
3 KiB
ReStructuredText
Verification
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============
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Overview
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--------
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This is a SV/UVM testbench for the ibex core verification.
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This testbench loads the instruction binary generated from open source random instruction generator `riscv-dv <https://github.com/google/riscv-dv>`_, runs the RTL simulation, and compares the instruction trace against ISS simulation.
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Testbench component
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~~~~~~~~~~~~~~~~~~~
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- Random instruction generator : `RISCV-DV <https://github.com/google/riscv-dv>`_
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- `Memory interface agent for instruction fetch and load/store
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operations <https://github.com/lowRISC/ibex/tree/master/dv/uvm/common/ibex_mem_intf_agent>`_
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- `Interrupt interface agent <https://github.com/lowRISC/ibex/tree/master/dv/uvm/common/irq_agent>`_
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- `Memory model <https://github.com/lowRISC/ibex/tree/master/dv/uvm/common/mem_model>`_
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- `Test and sequence library <https://github.com/lowRISC/ibex/tree/master/dv/uvm/tests>`_
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Testplan
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~~~~~~~~
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The goal of this bench is to fully verify the ibex core with 100%
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coverage. This includes all RV32IMC instructions testing, privileged
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spec compliance, exception and interrupt testing, debug mode operations
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etc. The complete test list can be found `here <https://github.com/lowRISC/ibex/blob/master/dv/uvm/riscv_dv_extension/testlist.yaml>`_.
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Please note that this work is still working in progress.
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Getting Started
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---------------
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Prerequisites
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~~~~~~~~~~~~~
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- VCS RTL simulator (need to support UVM 1.2)
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- `Setup the RISC-V instruction generator and ISS sim environment <https://github.com/google/riscv-dv#getting-started>`_
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End-to-end RTL/ISS co-simulation flow
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. figure:: images/dv-flow.png
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:alt: RTL/ISS co-simulation flow chart
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RTL/ISS co-simulation flow chart
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The flow is controlled by a `Makefile <https://github.com/lowRISC/ibex/blob/master/dv/uvm/Makefile>`_, here’s the list of frequently
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used commands:
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.. codeblock:: bash
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# Run a full regression
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make
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# Run a full regression, redirect the output directory
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make OUT=xxx
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# Run a single test
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make TEST=riscv_machine_mode_rand_test ITERATIONS=1
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# Run a test with a specific seed, dump waveform
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make TEST=riscv_machine_mode_rand_test ITERATIONS=1 SEED=123 WAVES=1
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# Verbose logging
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make ... VERBOSE=1
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# Run multipe tests in parallel through LSF
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make ... LSF_CMD="bsub -Is"
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# Get command reference of the simulation script
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python3 sim.py --help
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# Generate the assembly tests only
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make gen
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# Pass addtional options to the generator
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make GEN_OPTS="xxxx" ...
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# Compile and run RTL simulation
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make TEST=xxx compile,rtl_sim
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# Use a different ISS (default is spike)
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make ... ISS=ovpsim
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# Run a full regression with coverage
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make COV=1
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Run with a different RTL simulator
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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You can add the compile/simulation options in `simulator.yaml <https://github.com/lowRISC/ibex/blob/master/dv/uvm/yaml/rtl_simulation.yaml>`_.
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.. codeblock:: bash
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# Use the new RTL simulator to run
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make ... SIMULATOR=xxx
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