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Exact
Tom Roberts 44b033cf8b [rtl] Add support for instruction fetch errors 
- Add required signals to top-level
- Propagate error through fetch stages
- Add new exception type
- Update documentation for new exception type
- Resolves issue #109
2019-08-09 10:44:37 +01:00
..
rtl Example for Ibex tracer usage 2019-07-11 13:25:18 +01:00
tb [rtl] Add support for instruction fetch errors 2019-08-09 10:44:37 +01:00
README.md Rework how tracer is instantiated and called 2019-07-23 19:45:48 +01:00
top_tracing_sim.core Updates to the sim timescale option 2019-07-29 16:00:35 +01:00

README.md

Example: Ibex with enabled instruction tracing for simulation

Overview

This examples shows the usage of the module ibex_core_tracing which forwards all port signals to the ibex_core and a subset of signals to ibex_tracer. The tracer will create a file with a stream of executed instructions.

Prerequisites

For this example, modelsim must be available and the following environment variable must point to the path of installation:

export MODEL_TECH=/path/to/modelsim/bin

Usage

Run the following command in the top level directory.

fusesoc --cores-root=. run --target=sim lowrisc:ibex:top_tracing_sim

The trace output can be found in build/lowrisc_ibex_top_tracing_sim_0.1/sim-modelsim/trace_core_00_0.log.