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https://github.com/lowRISC/ibex.git
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187944c417
This commit includes switching to a scrambling RAM primitive for ICache data and tag RAMs. Also introduces minor changes to ICache to handle scrambling key valid signal. It also includes a minor bug fix regarding not initializing `fill_way_q` signal without ResetAll parameter. When the parameter is not set and we have our first hit right after ICache enables, the signal hangs. Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
22 lines
541 B
Text
22 lines
541 B
Text
CAPI=2:
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:ibex:ibex_icache:0.1"
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description: "Ibex instruction cache"
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filesets:
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files_rtl:
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depend:
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- lowrisc:prim:secded
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- lowrisc:prim:assert
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- lowrisc:ibex:ibex_pkg
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files:
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- rtl/ibex_icache.sv
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file_type: systemVerilogSource
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targets:
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default: &default_target
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filesets:
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- files_rtl
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toplevel: ibex_icache
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default_tool: vcs
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