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db926e5ef5
It turned out that with the default value of 1, Vivado infers a separate 18 Kbit BRAM instance for each bit of the 32-bit word for the FPGA examples. This can be very wasteful in terms of resource utilization especially for smaller configurations. As our examples don't use ECC or parity and mainly target simualation and FPGA, it's better to use a value of 8 for the DataBitsPerMask parameter. Vivado will then not distribute words across different BRAM instances which results in more efficient FPGA resource utilization. For a detailed analysis and explanation, please refer to lowRISC/Ibex#1587. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
91 lines
2.2 KiB
Systemverilog
91 lines
2.2 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Dual-port RAM with 1 cycle read/write delay, 32 bit words.
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*/
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`include "prim_assert.sv"
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module ram_2p #(
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parameter int Depth = 128,
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parameter MemInitFile = ""
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) (
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input clk_i,
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input rst_ni,
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input a_req_i,
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input a_we_i,
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input [ 3:0] a_be_i,
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input [31:0] a_addr_i,
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input [31:0] a_wdata_i,
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output logic a_rvalid_o,
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output logic [31:0] a_rdata_o,
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input b_req_i,
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input b_we_i,
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input [ 3:0] b_be_i,
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input [31:0] b_addr_i,
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input [31:0] b_wdata_i,
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output logic b_rvalid_o,
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output logic [31:0] b_rdata_o
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);
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localparam int Aw = $clog2(Depth);
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logic [Aw-1:0] a_addr_idx;
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assign a_addr_idx = a_addr_i[Aw-1+2:2];
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logic [31-Aw:0] unused_a_addr_parts;
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assign unused_a_addr_parts = {a_addr_i[31:Aw+2], a_addr_i[1:0]};
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logic [Aw-1:0] b_addr_idx;
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assign b_addr_idx = b_addr_i[Aw-1+2:2];
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logic [31-Aw:0] unused_b_addr_parts;
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assign unused_b_addr_parts = {b_addr_i[31:Aw+2], b_addr_i[1:0]};
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// Convert byte mask to SRAM bit mask.
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logic [31:0] a_wmask;
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logic [31:0] b_wmask;
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always_comb begin
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for (int i = 0 ; i < 4 ; i++) begin
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// mask for read data
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a_wmask[8*i+:8] = {8{a_be_i[i]}};
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b_wmask[8*i+:8] = {8{b_be_i[i]}};
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end
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end
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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a_rvalid_o <= '0;
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b_rvalid_o <= '0;
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end else begin
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a_rvalid_o <= a_req_i;
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b_rvalid_o <= b_req_i;
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end
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end
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prim_ram_2p #(
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.Width(32),
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.Depth(Depth),
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.DataBitsPerMask(8),
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.MemInitFile(MemInitFile)
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) u_ram (
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.clk_a_i (clk_i),
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.clk_b_i (clk_i),
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.cfg_i ('0),
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.a_req_i (a_req_i),
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.a_write_i (a_we_i),
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.a_addr_i (a_addr_idx),
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.a_wdata_i (a_wdata_i),
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.a_wmask_i (a_wmask),
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.a_rdata_o (a_rdata_o),
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.b_req_i (b_req_i),
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.b_write_i (b_we_i),
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.b_wmask_i (b_wmask),
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.b_addr_i (b_addr_idx),
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.b_wdata_i (b_wdata_i),
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.b_rdata_o (b_rdata_o)
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);
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endmodule
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