mirror of
https://github.com/lowRISC/ibex.git
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6a3200929b
This commit creates a new top level wrapping the core, register file and icache RAMs. The tracing top level is also renamed to ibex_top_tracing to match. This new top level is intended to enable a dual core lockstep implementation of Ibex. There are no functional changes in this commit, only wiring. Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
81 lines
2.7 KiB
Bash
Executable file
81 lines
2.7 KiB
Bash
Executable file
#!/bin/bash
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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# This script converts all SystemVerilog RTL files to Verilog
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# using sv2v and then runs LEC (Cadence Conformal) to check if
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# the generated Verilog is logically equivalent to the original
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# SystemVerilog. A similar script is used in OpenTitan, any updates
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# or fixes here may need to be reflected in the OpenTitan script as well
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# https://github.com/lowRISC/opentitan/blob/master/util/syn_yosys.sh
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#
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# The following tools are required:
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# - sv2v: SystemVerilog-to-Verilog converter from github.com/zachjs/sv2v
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# - Cadence Conformal
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#
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# Usage:
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# ./lec_sv2v.sh |& tee lec.log
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#-------------------------------------------------------------------------
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# use fusesoc to generate files and file list
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#-------------------------------------------------------------------------
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rm -Rf build lec_out
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fusesoc --cores-root .. run --tool=icarus --target=lint \
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--setup "lowrisc:ibex:ibex_top" > /dev/null 2>&1
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# copy all files to lec_out
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mkdir lec_out
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cp build/*/src/*/*.sv build/*/src/*/*/*.sv lec_out
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cd lec_out
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# copy file list and remove incdir, RVFI define, and sim-file
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egrep -v 'incdir|RVFI|simulator_ctrl' ../build/*/*/*.scr > flist_gold
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# remove all hierarchical paths
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sed -i 's!.*/!!' flist_gold
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# generate revised flist by replacing '.sv' by '.v' and removing packages
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sed 's/.sv/.v/' flist_gold | grep -v "_pkg.v" > flist_rev
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#-------------------------------------------------------------------------
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# convert all RTL files to Verilog using sv2v
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#-------------------------------------------------------------------------
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printf "\nSV2V ERRORS:\n"
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for file in *.sv; do
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module=`basename -s .sv $file`
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sv2v --define=SYNTHESIS *_pkg.sv prim_assert.sv $file > ${module}.v
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done
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# remove *pkg.v files (they are empty files and not needed)
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rm -f *_pkg.v prim_assert.v prim_util_memload.v
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# overwrite the prim_clock_gating modules with the module from ../rtl
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cp ../rtl/prim_clock_gating.v .
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cp ../rtl/prim_clock_gating.v prim_clock_gating.sv
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#-------------------------------------------------------------------------
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# run LEC (generated Verilog vs. original SystemVerilog)
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#-------------------------------------------------------------------------
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printf "\n\nLEC RESULTS:\n"
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for file in *.v; do
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export LEC_TOP=`basename -s .v $file`
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# run Conformal LEC
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lec -xl -nogui -nobanner \
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-dofile ../lec_sv2v.do \
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-logfile lec_${LEC_TOP}.log \
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<<< "exit -force" > /dev/null 2>&1
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# summarize results
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check=`grep "Compare Results" lec_${LEC_TOP}.log`
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if [ $? -ne 0 ]; then
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result="CRASH"
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else
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result=`echo $check | awk '{ print $4 }'`
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fi
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printf "%-25s %s\n" $LEC_TOP $result
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done
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