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Update code from upstream repository https://github.com/lowRISC/opentitan to revision 0747afbddec0ad176980429fe3100b32edb71d4a * [dv] Enable C/C++ code sourcing with VCS in .core (Canberk Topal) * [dv/dv_base_reg] Remove duplicated `get_map_by_name` method (Cindy Chen) * [prim] Pulse Sync assertion to check input/output (Eunchan Kim) * [sparse_fsm_flop] Create flop macro to increase DV coverage (Michael Schaffner) * [dvsim] Make build-randomization opt-in (Srikrishna Iyer) * [xcelium] Fix compile error (Srikrishna Iyer) * [dv/cov] fpv_csr_assert only collect assertion coverage (Cindy Chen) * [dv/jtag] Fix chip_level jtag csr rw failure (Cindy Chen) * [rtl] Convert some non-ANSI parameters to localparams (Rupert Swarbrick) * [prim] Waive unused parameters for Verilator in prim_generic_otp (Rupert Swarbrick) * [prim] Make a variable widening explicit in prim_present.sv (Rupert Swarbrick) * [prim] Waive some ALWCOMBORDER Verilator warnings in prim_arbiter_* (Rupert Swarbrick) * [prim] Fix Verilator lint warnings in prim_gf_mult.sv (Rupert Swarbrick) * [prim] Make some widening comparisons explicit in prim_clock_*.sv (Rupert Swarbrick) * [prim] Waive unused EnableAlertTriggerSVA for verilator lint (Rupert Swarbrick) * [bazel,dvsim] Add build rules for dvsim.py (Timothy Trippel) * [prim] Fix a bunch of Verilator lint errors in prim_packer.sv (Rupert Swarbrick) * [prim_sparse_fsm_flop/lint] Move waiver to correct file (Michael Schaffner) * [rv_dm dv] Test drive compile-time seed (Srikrishna Iyer) * [dvsim] Introduce Verilog compile-time seeds (Srikrishna Iyer) * [dvsim] Treat `tests: ["N/A"]` as an ignored testpoint (Srikrishna Iyer) * [hw/dv] Removed colon from Questa build and run fail patterns. (David Pudner) * [hw/dv] Code review changes for running questa simulations. (David Pudner) * [hw/dv] Added apache license header to questa_initial_setup.sh. (David Pudner) * [doc/ug] Updated opentitan documentation to include information about Questa use. (David Pudner) * [hw/dv] Added Questa dvsim files (David Pudner) * [dv/unr] Blackbox common security modules from UNR flow (Cindy Chen) * [dv] Minor fix to error message in mem_model.sv (Rupert Swarbrick) * [keymgr] Update keymgr to use prim_edn_req (Timothy Chen) * [doc] Fix rendering of special characters in testplan table (Rupert Swarbrick) * [dv] enable tlul_assert for csr part2 (Rasmus Madsen) * [dv] Enable tlul_assert for CSR tests (Weicai Yang) * [dv] Add valid/ready req/ack coverage for push_pull agent (Weicai Yang) * [dv,verilator] Make multiple sim_ctrl extensions play nicely (Rupert Swarbrick) * [chip dv] Add AST initialization routine (Srikrishna Iyer) * [top] auto generate (Timothy Chen) * [reggen] Make field 'qe' behavior consistent (Timothy Chen) * [prim] IFDEF_CODE waiver in sparsefsm flop (Eunchan Kim) * [dv] Update checklist for all blocks (Weicai Yang) * [dv/entropy_src] Temp remove stress_all_with_rand_reset test (Cindy Chen) Signed-off-by: Canberk Topal <ctopal@lowrisc.org> |
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