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Rupert Swarbrick 96cf24a41a Add a stress_all_with_reset ICache test 
This is like the stress_all test, picking other sequences at random
and running them back-to-back. The difference is in the reset
behaviour, where we randomly pull the reset line at unexpected times
to try to trigger any strange glitches this might cause.

This requires slight changes to the core and memory drivers, which
need to learn to stop and return early from the current item when they
see a reset.
2020-06-22 17:11:59 +01:00
..
ibex_icache_testplan.hjson Add a stress_all_with_reset ICache test 2020-06-22 17:11:59 +01:00