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https://github.com/lowRISC/ibex.git
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5bb41957ef
Not particularly useful in the current system, but gives an example of how to handle interrupts.
102 lines
1.7 KiB
ArmAsm
102 lines
1.7 KiB
ArmAsm
# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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#include "simple_system_regs.h"
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.section .text
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default_exc_handler:
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jal x0, simple_exc_handler
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timer_handler:
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jal x0, simple_timer_handler
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reset_handler:
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/* set all registers to zero */
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mv x1, x0
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mv x2, x1
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mv x3, x1
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mv x4, x1
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mv x5, x1
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mv x6, x1
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mv x7, x1
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mv x8, x1
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mv x9, x1
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mv x10, x1
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mv x11, x1
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mv x12, x1
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mv x13, x1
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mv x14, x1
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mv x15, x1
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mv x16, x1
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mv x17, x1
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mv x18, x1
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mv x19, x1
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mv x20, x1
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mv x21, x1
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mv x22, x1
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mv x23, x1
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mv x24, x1
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mv x25, x1
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mv x26, x1
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mv x27, x1
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mv x28, x1
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mv x29, x1
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mv x30, x1
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mv x31, x1
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/* stack initilization */
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la x2, _stack_start
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_start:
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.global _start
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/* clear BSS */
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la x26, _bss_start
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la x27, _bss_end
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bge x26, x27, zero_loop_end
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zero_loop:
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sw x0, 0(x26)
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addi x26, x26, 4
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ble x26, x27, zero_loop
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zero_loop_end:
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main_entry:
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/* jump to main program entry point (argc = argv = 0) */
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addi x10, x0, 0
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addi x11, x0, 0
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jal x1, main
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/* Halt simulation */
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li x5, SIM_CTRL_BASE + SIM_CTRL_CTRL
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li x6, 1
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sw x6, 0(x5)
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/* If execution ends up here just put the core to sleep */
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sleep_loop:
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wfi
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j sleep_loop
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/* =================================================== [ exceptions ] === */
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/* This section has to be down here, since we have to disable rvc for it */
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.section .vectors, "ax"
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.option norvc;
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// All unimplemented interrupts/exceptions go to the default_exc_handler.
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.org 0x00
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.rept 7
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jal x0, default_exc_handler
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.endr
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jal x0, timer_handler
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.rept 23
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jal x0, default_exc_handler
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.endr
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// reset vector
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.org 0x80
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jal x0, reset_handler
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