mirror of
https://github.com/lowRISC/ibex.git
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1451 lines
57 KiB
Systemverilog
1451 lines
57 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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`ifdef RISCV_FORMAL
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`define RVFI
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`endif
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`include "prim_assert.sv"
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`ifndef RV32B
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`define RV32B ibex_pkg::RV32BNone
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`endif
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/**
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* Top level module of the ibex RISC-V core
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*/
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module ibex_core #(
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parameter bit PMPEnable = 1'b0,
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parameter int unsigned PMPGranularity = 0,
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parameter int unsigned PMPNumRegions = 4,
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parameter int unsigned MHPMCounterNum = 0,
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parameter int unsigned MHPMCounterWidth = 40,
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parameter bit RV32E = 1'b0,
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parameter bit RV32M = 1'b1,
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parameter ibex_pkg::rv32b_e RV32B = `RV32B,
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parameter bit BranchTargetALU = 1'b0,
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parameter bit WritebackStage = 1'b0,
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parameter MultiplierImplementation = "fast",
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parameter bit ICache = 1'b0,
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parameter bit ICacheECC = 1'b0,
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parameter bit DbgTriggerEn = 1'b0,
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parameter bit SecureIbex = 1'b0,
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parameter int unsigned DmHaltAddr = 32'h1A110800,
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parameter int unsigned DmExceptionAddr = 32'h1A110808,
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parameter bit PointerAuthentication = 1'b0
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) (
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// Clock and Reset
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input logic clk_i,
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input logic rst_ni,
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input logic test_en_i, // enable all clock gates for testing
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input logic [31:0] hart_id_i,
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input logic [31:0] boot_addr_i,
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// Instruction memory interface
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output logic instr_req_o,
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input logic instr_gnt_i,
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input logic instr_rvalid_i,
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output logic [31:0] instr_addr_o,
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input logic [31:0] instr_rdata_i,
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input logic instr_err_i,
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// Data memory interface
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output logic data_req_o,
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input logic data_gnt_i,
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input logic data_rvalid_i,
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output logic data_we_o,
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output logic [3:0] data_be_o,
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output logic [31:0] data_addr_o,
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output logic [31:0] data_wdata_o,
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input logic [31:0] data_rdata_i,
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input logic data_err_i,
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// Interrupt inputs
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input logic irq_software_i,
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input logic irq_timer_i,
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input logic irq_external_i,
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input logic [14:0] irq_fast_i,
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input logic irq_nm_i, // non-maskeable interrupt
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// Debug Interface
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input logic debug_req_i,
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// RISC-V Formal Interface
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// Does not comply with the coding standards of _i/_o suffixes, but follows
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// the convention of RISC-V Formal Interface Specification.
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`ifdef RVFI
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output logic rvfi_valid,
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output logic [63:0] rvfi_order,
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output logic [31:0] rvfi_insn,
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output logic rvfi_trap,
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output logic rvfi_halt,
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output logic rvfi_intr,
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output logic [ 1:0] rvfi_mode,
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output logic [ 1:0] rvfi_ixl,
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output logic [ 4:0] rvfi_rs1_addr,
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output logic [ 4:0] rvfi_rs2_addr,
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output logic [ 4:0] rvfi_rs3_addr,
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output logic [31:0] rvfi_rs1_rdata,
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output logic [31:0] rvfi_rs2_rdata,
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output logic [31:0] rvfi_rs3_rdata,
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output logic [ 4:0] rvfi_rd_addr,
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output logic [31:0] rvfi_rd_wdata,
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output logic [31:0] rvfi_pc_rdata,
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output logic [31:0] rvfi_pc_wdata,
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output logic [31:0] rvfi_mem_addr,
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output logic [ 3:0] rvfi_mem_rmask,
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output logic [ 3:0] rvfi_mem_wmask,
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output logic [31:0] rvfi_mem_rdata,
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output logic [31:0] rvfi_mem_wdata,
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`endif
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// CPU Control Signals
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input logic fetch_enable_i,
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output logic alert_minor_o,
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output logic alert_major_o,
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output logic core_sleep_o
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);
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import ibex_pkg::*;
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localparam int unsigned PMP_NUM_CHAN = 2;
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localparam bit DataIndTiming = SecureIbex;
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localparam bit DummyInstructions = SecureIbex;
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// Speculative branch option, trades-off performance against timing.
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// Setting this to 1 eases branch target critical paths significantly but reduces performance
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// by ~3% (based on CoreMark/MHz score).
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// Set by default in the max PMP config which has the tightest budget for branch target timing.
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localparam bit SpecBranch = PMPEnable & (PMPNumRegions == 16);
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localparam bit RegFileECC = SecureIbex;
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localparam int unsigned RegFileDataWidth = RegFileECC ? 32 + 7 : 32;
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// IF/ID signals
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logic dummy_instr_id;
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logic instr_valid_id;
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logic instr_new_id;
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logic [31:0] instr_rdata_id; // Instruction sampled inside IF stage
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logic [31:0] instr_rdata_alu_id; // Instruction sampled inside IF stage (replicated to
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// ease fan-out)
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logic [15:0] instr_rdata_c_id; // Compressed instruction sampled inside IF stage
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logic instr_is_compressed_id;
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logic instr_fetch_err; // Bus error on instr fetch
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logic instr_fetch_err_plus2; // Instruction error is misaligned
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logic illegal_c_insn_id; // Illegal compressed instruction sent to ID stage
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logic [31:0] pc_if; // Program counter in IF stage
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logic [31:0] pc_id; // Program counter in ID stage
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logic [31:0] pc_wb; // Program counter in WB stage
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logic [33:0] imd_val_d_ex[2]; // Intermediate register for multicycle Ops
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logic [33:0] imd_val_q_ex[2]; // Intermediate register for multicycle Ops
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logic [1:0] imd_val_we_ex;
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logic data_ind_timing;
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logic dummy_instr_en;
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logic [2:0] dummy_instr_mask;
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logic dummy_instr_seed_en;
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logic [31:0] dummy_instr_seed;
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logic icache_enable;
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logic icache_inval;
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logic instr_first_cycle_id;
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logic instr_valid_clear;
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logic pc_set;
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logic pc_set_spec;
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pc_sel_e pc_mux_id; // Mux selector for next PC
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exc_pc_sel_e exc_pc_mux_id; // Mux selector for exception PC
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exc_cause_e exc_cause; // Exception cause
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logic lsu_load_err;
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logic lsu_store_err;
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// LSU signals
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logic lsu_addr_incr_req;
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logic [31:0] lsu_addr_last;
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// Jump and branch target and decision (EX->IF)
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logic [31:0] branch_target_ex;
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logic branch_decision;
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// Core busy signals
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logic ctrl_busy;
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logic if_busy;
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logic lsu_busy;
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logic core_busy_d, core_busy_q;
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// Register File
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logic [4:0] rf_raddr_a;
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logic [31:0] rf_rdata_a;
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logic [4:0] rf_raddr_b;
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logic [31:0] rf_rdata_b;
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logic rf_ren_a;
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logic rf_ren_b;
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logic [4:0] rf_waddr_wb;
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logic [31:0] rf_wdata_wb;
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// Writeback register write data that can be used on the forwarding path (doesn't factor in memory
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// read data as this is too late for the forwarding path)
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logic [31:0] rf_wdata_fwd_wb;
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logic [31:0] rf_wdata_lsu;
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logic rf_we_wb;
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logic rf_we_lsu;
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logic [4:0] rf_waddr_id;
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logic [31:0] rf_wdata_id;
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logic rf_we_id;
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logic rf_rd_a_wb_match;
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logic rf_rd_b_wb_match;
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// ALU Control
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alu_op_e alu_operator_ex;
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logic [31:0] alu_operand_a_ex;
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logic [31:0] alu_operand_b_ex;
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logic [31:0] bt_a_operand;
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logic [31:0] bt_b_operand;
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logic [31:0] alu_adder_result_ex; // Used to forward computed address to LSU
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logic [31:0] result_ex;
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// Multiplier Control
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logic mult_en_ex;
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logic div_en_ex;
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logic mult_sel_ex;
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logic div_sel_ex;
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md_op_e multdiv_operator_ex;
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logic [1:0] multdiv_signed_mode_ex;
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logic [31:0] multdiv_operand_a_ex;
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logic [31:0] multdiv_operand_b_ex;
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logic multdiv_ready_id;
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// CSR control
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logic csr_access;
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csr_op_e csr_op;
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logic csr_op_en;
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csr_num_e csr_addr;
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logic [31:0] csr_rdata;
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logic [31:0] csr_wdata;
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logic illegal_csr_insn_id; // CSR access to non-existent register,
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// with wrong priviledge level,
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// or missing write permissions
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// Data Memory Control
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logic lsu_we;
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logic [1:0] lsu_type;
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logic lsu_sign_ext;
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logic lsu_req;
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logic [31:0] lsu_wdata;
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logic lsu_req_done;
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// stall control
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logic id_in_ready;
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logic ex_valid;
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logic lsu_resp_valid;
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// Signals between instruction core interface and pipe (if and id stages)
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logic instr_req_int; // Id stage asserts a req to instruction core interface
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// Writeback stage
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logic en_wb;
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wb_instr_type_e instr_type_wb;
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logic ready_wb;
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logic rf_write_wb;
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logic outstanding_load_wb;
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logic outstanding_store_wb;
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// Interrupts
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logic irq_pending;
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logic nmi_mode;
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irqs_t irqs;
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logic csr_mstatus_mie;
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logic [31:0] csr_mepc, csr_depc;
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// PMP signals
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logic [33:0] csr_pmp_addr [PMPNumRegions];
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pmp_cfg_t csr_pmp_cfg [PMPNumRegions];
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logic pmp_req_err [PMP_NUM_CHAN];
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logic instr_req_out;
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logic data_req_out;
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logic csr_save_if;
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logic csr_save_id;
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logic csr_save_wb;
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logic csr_restore_mret_id;
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logic csr_restore_dret_id;
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logic csr_save_cause;
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logic csr_mtvec_init;
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logic [31:0] csr_mtvec;
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logic [31:0] csr_mtval;
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logic csr_mstatus_tw;
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priv_lvl_e priv_mode_id;
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priv_lvl_e priv_mode_if;
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priv_lvl_e priv_mode_lsu;
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// debug mode and dcsr configuration
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logic debug_mode;
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dbg_cause_e debug_cause;
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logic debug_csr_save;
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logic debug_single_step;
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logic debug_ebreakm;
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logic debug_ebreaku;
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logic trigger_match;
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// signals relating to instruction movements between pipeline stages
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// used by performance counters and RVFI
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logic instr_id_done;
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logic instr_id_done_compressed;
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logic instr_done_wb;
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logic perf_iside_wait;
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logic perf_dside_wait;
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logic perf_mul_wait;
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logic perf_div_wait;
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logic perf_jump;
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logic perf_branch;
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logic perf_tbranch;
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logic perf_load;
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logic perf_store;
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logic perf_pac;
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logic perf_aut;
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// for RVFI
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logic illegal_insn_id, unused_illegal_insn_id; // ID stage sees an illegal instruction
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// RISC-V Formal Interface signals
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`ifdef RVFI
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logic rvfi_instr_new_wb;
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logic rvfi_intr_d;
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logic rvfi_intr_q;
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logic rvfi_set_trap_pc_d;
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logic rvfi_set_trap_pc_q;
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logic [31:0] rvfi_insn_id;
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logic [4:0] rvfi_rs1_addr_d;
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logic [4:0] rvfi_rs1_addr_q;
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logic [4:0] rvfi_rs2_addr_d;
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logic [4:0] rvfi_rs2_addr_q;
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logic [4:0] rvfi_rs3_addr_d;
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logic [31:0] rvfi_rs1_data_d;
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logic [31:0] rvfi_rs1_data_q;
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logic [31:0] rvfi_rs2_data_d;
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logic [31:0] rvfi_rs2_data_q;
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logic [31:0] rvfi_rs3_data_d;
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logic [4:0] rvfi_rd_addr_wb;
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logic [4:0] rvfi_rd_addr_q;
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logic [4:0] rvfi_rd_addr_d;
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logic [31:0] rvfi_rd_wdata_wb;
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logic [31:0] rvfi_rd_wdata_d;
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logic [31:0] rvfi_rd_wdata_q;
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logic rvfi_rd_we_wb;
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logic [3:0] rvfi_mem_mask_int;
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logic [31:0] rvfi_mem_rdata_d;
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logic [31:0] rvfi_mem_rdata_q;
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logic [31:0] rvfi_mem_wdata_d;
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logic [31:0] rvfi_mem_wdata_q;
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logic [31:0] rvfi_mem_addr_d;
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logic [31:0] rvfi_mem_addr_q;
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`endif
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// Pointer Authentication
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logic pa_pac_en;
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logic pa_aut_en;
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logic [31:0] pa_data0;
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logic [31:0] pa_data1;
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logic pa_ready_id;
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logic [31:0] pa_result;
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logic pa_valid;
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logic [127:0] csr_pa_key;
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//////////////////////
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// Clock management //
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//////////////////////
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logic clk;
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logic clock_en;
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// Before going to sleep, wait for I- and D-side
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// interfaces to finish ongoing operations.
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assign core_busy_d = ctrl_busy | if_busy | lsu_busy;
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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core_busy_q <= 1'b0;
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end else begin
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core_busy_q <= core_busy_d;
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end
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end
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// capture fetch_enable_i in fetch_enable_q, once for ever
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logic fetch_enable_q;
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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fetch_enable_q <= 1'b0;
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end else if (fetch_enable_i) begin
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fetch_enable_q <= 1'b1;
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end
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end
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assign clock_en = fetch_enable_q & (core_busy_q | debug_req_i | irq_pending | irq_nm_i);
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assign core_sleep_o = ~clock_en;
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// main clock gate of the core
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// generates all clocks except the one for the debug unit which is
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// independent
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prim_clock_gating core_clock_gate_i (
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.clk_i ( clk_i ),
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.en_i ( clock_en ),
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.test_en_i ( test_en_i ),
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.clk_o ( clk )
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);
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//////////////
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// IF stage //
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//////////////
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ibex_if_stage #(
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.DmHaltAddr ( DmHaltAddr ),
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.DmExceptionAddr ( DmExceptionAddr ),
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.DummyInstructions ( DummyInstructions ),
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.ICache ( ICache ),
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.ICacheECC ( ICacheECC )
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) if_stage_i (
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.clk_i ( clk ),
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.rst_ni ( rst_ni ),
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.boot_addr_i ( boot_addr_i ),
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.req_i ( instr_req_int ), // instruction request control
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// instruction cache interface
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.instr_req_o ( instr_req_out ),
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.instr_addr_o ( instr_addr_o ),
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.instr_gnt_i ( instr_gnt_i ),
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.instr_rvalid_i ( instr_rvalid_i ),
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.instr_rdata_i ( instr_rdata_i ),
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.instr_err_i ( instr_err_i ),
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.instr_pmp_err_i ( pmp_req_err[PMP_I] ),
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// outputs to ID stage
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.instr_valid_id_o ( instr_valid_id ),
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.instr_new_id_o ( instr_new_id ),
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.instr_rdata_id_o ( instr_rdata_id ),
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.instr_rdata_alu_id_o ( instr_rdata_alu_id ),
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.instr_rdata_c_id_o ( instr_rdata_c_id ),
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.instr_is_compressed_id_o ( instr_is_compressed_id ),
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.instr_fetch_err_o ( instr_fetch_err ),
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.instr_fetch_err_plus2_o ( instr_fetch_err_plus2 ),
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.illegal_c_insn_id_o ( illegal_c_insn_id ),
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.dummy_instr_id_o ( dummy_instr_id ),
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.pc_if_o ( pc_if ),
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.pc_id_o ( pc_id ),
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// control signals
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.instr_valid_clear_i ( instr_valid_clear ),
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.pc_set_i ( pc_set ),
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.pc_set_spec_i ( pc_set_spec ),
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.pc_mux_i ( pc_mux_id ),
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.exc_pc_mux_i ( exc_pc_mux_id ),
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.exc_cause ( exc_cause ),
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.dummy_instr_en_i ( dummy_instr_en ),
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.dummy_instr_mask_i ( dummy_instr_mask ),
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.dummy_instr_seed_en_i ( dummy_instr_seed_en ),
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.dummy_instr_seed_i ( dummy_instr_seed ),
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.icache_enable_i ( icache_enable ),
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.icache_inval_i ( icache_inval ),
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// branch targets
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.branch_target_ex_i ( branch_target_ex ),
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// CSRs
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.csr_mepc_i ( csr_mepc ), // exception return address
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.csr_depc_i ( csr_depc ), // debug return address
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.csr_mtvec_i ( csr_mtvec ), // trap-vector base address
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.csr_mtvec_init_o ( csr_mtvec_init ),
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// pipeline stalls
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.id_in_ready_i ( id_in_ready ),
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.if_busy_o ( if_busy )
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);
|
|
|
|
// Core is waiting for the ISide when ID/EX stage is ready for a new instruction but none are
|
|
// available
|
|
assign perf_iside_wait = id_in_ready & ~instr_valid_id;
|
|
|
|
// Qualify the instruction request with PMP error
|
|
assign instr_req_o = instr_req_out & ~pmp_req_err[PMP_I];
|
|
|
|
//////////////
|
|
// ID stage //
|
|
//////////////
|
|
|
|
ibex_id_stage #(
|
|
.RV32E ( RV32E ),
|
|
.RV32M ( RV32M ),
|
|
.RV32B ( RV32B ),
|
|
.BranchTargetALU ( BranchTargetALU ),
|
|
.DataIndTiming ( DataIndTiming ),
|
|
.SpecBranch ( SpecBranch ),
|
|
.WritebackStage ( WritebackStage ),
|
|
.PointerAuthentication ( PointerAuthentication )
|
|
) id_stage_i (
|
|
.clk_i ( clk ),
|
|
.rst_ni ( rst_ni ),
|
|
|
|
// Processor Enable
|
|
.ctrl_busy_o ( ctrl_busy ),
|
|
.illegal_insn_o ( illegal_insn_id ),
|
|
|
|
// from/to IF-ID pipeline register
|
|
.instr_valid_i ( instr_valid_id ),
|
|
.instr_rdata_i ( instr_rdata_id ),
|
|
.instr_rdata_alu_i ( instr_rdata_alu_id ),
|
|
.instr_rdata_c_i ( instr_rdata_c_id ),
|
|
.instr_is_compressed_i ( instr_is_compressed_id ),
|
|
|
|
// Jumps and branches
|
|
.branch_decision_i ( branch_decision ),
|
|
|
|
// IF and ID control signals
|
|
.instr_first_cycle_id_o ( instr_first_cycle_id ),
|
|
.instr_valid_clear_o ( instr_valid_clear ),
|
|
.id_in_ready_o ( id_in_ready ),
|
|
.instr_req_o ( instr_req_int ),
|
|
.pc_set_o ( pc_set ),
|
|
.pc_set_spec_o ( pc_set_spec ),
|
|
.pc_mux_o ( pc_mux_id ),
|
|
.exc_pc_mux_o ( exc_pc_mux_id ),
|
|
.exc_cause_o ( exc_cause ),
|
|
.icache_inval_o ( icache_inval ),
|
|
|
|
.instr_fetch_err_i ( instr_fetch_err ),
|
|
.instr_fetch_err_plus2_i ( instr_fetch_err_plus2 ),
|
|
.illegal_c_insn_i ( illegal_c_insn_id ),
|
|
|
|
.pc_id_i ( pc_id ),
|
|
|
|
// Stalls
|
|
.ex_valid_i ( ex_valid ),
|
|
.lsu_resp_valid_i ( lsu_resp_valid ),
|
|
|
|
.alu_operator_ex_o ( alu_operator_ex ),
|
|
.alu_operand_a_ex_o ( alu_operand_a_ex ),
|
|
.alu_operand_b_ex_o ( alu_operand_b_ex ),
|
|
|
|
.imd_val_q_ex_o ( imd_val_q_ex ),
|
|
.imd_val_d_ex_i ( imd_val_d_ex ),
|
|
.imd_val_we_ex_i ( imd_val_we_ex ),
|
|
|
|
.bt_a_operand_o ( bt_a_operand ),
|
|
.bt_b_operand_o ( bt_b_operand ),
|
|
|
|
.mult_en_ex_o ( mult_en_ex ),
|
|
.div_en_ex_o ( div_en_ex ),
|
|
.mult_sel_ex_o ( mult_sel_ex ),
|
|
.div_sel_ex_o ( div_sel_ex ),
|
|
.multdiv_operator_ex_o ( multdiv_operator_ex ),
|
|
.multdiv_signed_mode_ex_o ( multdiv_signed_mode_ex ),
|
|
.multdiv_operand_a_ex_o ( multdiv_operand_a_ex ),
|
|
.multdiv_operand_b_ex_o ( multdiv_operand_b_ex ),
|
|
.multdiv_ready_id_o ( multdiv_ready_id ),
|
|
|
|
// CSR ID/EX
|
|
.csr_access_o ( csr_access ),
|
|
.csr_op_o ( csr_op ),
|
|
.csr_op_en_o ( csr_op_en ),
|
|
.csr_save_if_o ( csr_save_if ), // control signal to save PC
|
|
.csr_save_id_o ( csr_save_id ), // control signal to save PC
|
|
.csr_save_wb_o ( csr_save_wb ), // control signal to save PC
|
|
.csr_restore_mret_id_o ( csr_restore_mret_id ), // restore mstatus upon MRET
|
|
.csr_restore_dret_id_o ( csr_restore_dret_id ), // restore mstatus upon MRET
|
|
.csr_save_cause_o ( csr_save_cause ),
|
|
.csr_mtval_o ( csr_mtval ),
|
|
.priv_mode_i ( priv_mode_id ),
|
|
.csr_mstatus_tw_i ( csr_mstatus_tw ),
|
|
.illegal_csr_insn_i ( illegal_csr_insn_id ),
|
|
.data_ind_timing_i ( data_ind_timing ),
|
|
|
|
// LSU
|
|
.lsu_req_o ( lsu_req ), // to load store unit
|
|
.lsu_we_o ( lsu_we ), // to load store unit
|
|
.lsu_type_o ( lsu_type ), // to load store unit
|
|
.lsu_sign_ext_o ( lsu_sign_ext ), // to load store unit
|
|
.lsu_wdata_o ( lsu_wdata ), // to load store unit
|
|
.lsu_req_done_i ( lsu_req_done ), // from load store unit
|
|
|
|
.lsu_addr_incr_req_i ( lsu_addr_incr_req ),
|
|
.lsu_addr_last_i ( lsu_addr_last ),
|
|
|
|
.lsu_load_err_i ( lsu_load_err ),
|
|
.lsu_store_err_i ( lsu_store_err ),
|
|
|
|
// Interrupt Signals
|
|
.csr_mstatus_mie_i ( csr_mstatus_mie ),
|
|
.irq_pending_i ( irq_pending ),
|
|
.irqs_i ( irqs ),
|
|
.irq_nm_i ( irq_nm_i ),
|
|
.nmi_mode_o ( nmi_mode ),
|
|
|
|
// Debug Signal
|
|
.debug_mode_o ( debug_mode ),
|
|
.debug_cause_o ( debug_cause ),
|
|
.debug_csr_save_o ( debug_csr_save ),
|
|
.debug_req_i ( debug_req_i ),
|
|
.debug_single_step_i ( debug_single_step ),
|
|
.debug_ebreakm_i ( debug_ebreakm ),
|
|
.debug_ebreaku_i ( debug_ebreaku ),
|
|
.trigger_match_i ( trigger_match ),
|
|
|
|
// write data to commit in the register file
|
|
.result_ex_i ( result_ex ),
|
|
.csr_rdata_i ( csr_rdata ),
|
|
|
|
.rf_raddr_a_o ( rf_raddr_a ),
|
|
.rf_rdata_a_i ( rf_rdata_a ),
|
|
.rf_raddr_b_o ( rf_raddr_b ),
|
|
.rf_rdata_b_i ( rf_rdata_b ),
|
|
.rf_ren_a_o ( rf_ren_a ),
|
|
.rf_ren_b_o ( rf_ren_b ),
|
|
.rf_waddr_id_o ( rf_waddr_id ),
|
|
.rf_wdata_id_o ( rf_wdata_id ),
|
|
.rf_we_id_o ( rf_we_id ),
|
|
.rf_rd_a_wb_match_o ( rf_rd_a_wb_match ),
|
|
.rf_rd_b_wb_match_o ( rf_rd_b_wb_match ),
|
|
|
|
.rf_waddr_wb_i ( rf_waddr_wb ),
|
|
.rf_wdata_fwd_wb_i ( rf_wdata_fwd_wb ),
|
|
.rf_write_wb_i ( rf_write_wb ),
|
|
|
|
.en_wb_o ( en_wb ),
|
|
.instr_type_wb_o ( instr_type_wb ),
|
|
.ready_wb_i ( ready_wb ),
|
|
.outstanding_load_wb_i ( outstanding_load_wb ),
|
|
.outstanding_store_wb_i ( outstanding_store_wb ),
|
|
|
|
// Performance Counters
|
|
.perf_jump_o ( perf_jump ),
|
|
.perf_branch_o ( perf_branch ),
|
|
.perf_tbranch_o ( perf_tbranch ),
|
|
.perf_dside_wait_o ( perf_dside_wait ),
|
|
.perf_mul_wait_o ( perf_mul_wait ),
|
|
.perf_div_wait_o ( perf_div_wait ),
|
|
.instr_id_done_o ( instr_id_done ),
|
|
.perf_pac_o ( perf_pac ),
|
|
.perf_aut_o ( perf_aut ),
|
|
.instr_id_done_compressed_o ( instr_id_done_compressed ),
|
|
|
|
// Pointer Authentication
|
|
.pac_en_id_o ( pa_pac_en ),
|
|
.aut_en_id_o ( pa_aut_en ),
|
|
.pa_data0_o ( pa_data0 ),
|
|
.pa_data1_o ( pa_data1 ),
|
|
.pa_ready_id_o ( pa_ready_id ),
|
|
.pa_result_i ( pa_result ),
|
|
.pa_valid_i ( pa_valid )
|
|
);
|
|
|
|
// for RVFI only
|
|
assign unused_illegal_insn_id = illegal_insn_id;
|
|
|
|
ibex_ex_block #(
|
|
.RV32M ( RV32M ),
|
|
.RV32B ( RV32B ),
|
|
.BranchTargetALU ( BranchTargetALU ),
|
|
.MultiplierImplementation ( MultiplierImplementation )
|
|
) ex_block_i (
|
|
.clk_i ( clk ),
|
|
.rst_ni ( rst_ni ),
|
|
|
|
// ALU signal from ID stage
|
|
.alu_operator_i ( alu_operator_ex ),
|
|
.alu_operand_a_i ( alu_operand_a_ex ),
|
|
.alu_operand_b_i ( alu_operand_b_ex ),
|
|
.alu_instr_first_cycle_i ( instr_first_cycle_id ),
|
|
|
|
// Branch target ALU signal from ID stage
|
|
.bt_a_operand_i ( bt_a_operand ),
|
|
.bt_b_operand_i ( bt_b_operand ),
|
|
|
|
// Multipler/Divider signal from ID stage
|
|
.multdiv_operator_i ( multdiv_operator_ex ),
|
|
.mult_en_i ( mult_en_ex ),
|
|
.div_en_i ( div_en_ex ),
|
|
.mult_sel_i ( mult_sel_ex ),
|
|
.div_sel_i ( div_sel_ex ),
|
|
.multdiv_signed_mode_i ( multdiv_signed_mode_ex ),
|
|
.multdiv_operand_a_i ( multdiv_operand_a_ex ),
|
|
.multdiv_operand_b_i ( multdiv_operand_b_ex ),
|
|
.multdiv_ready_id_i ( multdiv_ready_id ),
|
|
.data_ind_timing_i ( data_ind_timing ),
|
|
|
|
// Intermediate value register
|
|
.imd_val_we_o ( imd_val_we_ex ),
|
|
.imd_val_d_o ( imd_val_d_ex ),
|
|
.imd_val_q_i ( imd_val_q_ex ),
|
|
|
|
// Outputs
|
|
.alu_adder_result_ex_o ( alu_adder_result_ex ), // to LSU
|
|
.result_ex_o ( result_ex ), // to ID
|
|
|
|
.branch_target_o ( branch_target_ex ), // to IF
|
|
.branch_decision_o ( branch_decision ), // to ID
|
|
|
|
.ex_valid_o ( ex_valid )
|
|
);
|
|
|
|
/////////////////////
|
|
// Load/store unit //
|
|
/////////////////////
|
|
|
|
assign data_req_o = data_req_out & ~pmp_req_err[PMP_D];
|
|
|
|
ibex_load_store_unit load_store_unit_i (
|
|
.clk_i ( clk ),
|
|
.rst_ni ( rst_ni ),
|
|
|
|
// data interface
|
|
.data_req_o ( data_req_out ),
|
|
.data_gnt_i ( data_gnt_i ),
|
|
.data_rvalid_i ( data_rvalid_i ),
|
|
.data_err_i ( data_err_i ),
|
|
.data_pmp_err_i ( pmp_req_err[PMP_D] ),
|
|
|
|
.data_addr_o ( data_addr_o ),
|
|
.data_we_o ( data_we_o ),
|
|
.data_be_o ( data_be_o ),
|
|
.data_wdata_o ( data_wdata_o ),
|
|
.data_rdata_i ( data_rdata_i ),
|
|
|
|
// signals to/from ID/EX stage
|
|
.lsu_we_i ( lsu_we ),
|
|
.lsu_type_i ( lsu_type ),
|
|
.lsu_wdata_i ( lsu_wdata ),
|
|
.lsu_sign_ext_i ( lsu_sign_ext ),
|
|
|
|
.lsu_rdata_o ( rf_wdata_lsu ),
|
|
.lsu_rdata_valid_o ( rf_we_lsu ),
|
|
.lsu_req_i ( lsu_req ),
|
|
.lsu_req_done_o ( lsu_req_done ),
|
|
|
|
.adder_result_ex_i ( alu_adder_result_ex ),
|
|
|
|
.addr_incr_req_o ( lsu_addr_incr_req ),
|
|
.addr_last_o ( lsu_addr_last ),
|
|
|
|
|
|
.lsu_resp_valid_o ( lsu_resp_valid ),
|
|
|
|
// exception signals
|
|
.load_err_o ( lsu_load_err ),
|
|
.store_err_o ( lsu_store_err ),
|
|
|
|
.busy_o ( lsu_busy ),
|
|
|
|
.perf_load_o ( perf_load ),
|
|
.perf_store_o ( perf_store )
|
|
);
|
|
|
|
ibex_wb_stage #(
|
|
.WritebackStage ( WritebackStage )
|
|
) wb_stage_i (
|
|
.clk_i ( clk ),
|
|
.rst_ni ( rst_ni ),
|
|
.en_wb_i ( en_wb ),
|
|
.instr_type_wb_i ( instr_type_wb ),
|
|
.pc_id_i ( pc_id ),
|
|
|
|
.ready_wb_o ( ready_wb ),
|
|
.rf_write_wb_o ( rf_write_wb ),
|
|
.outstanding_load_wb_o ( outstanding_load_wb ),
|
|
.outstanding_store_wb_o ( outstanding_store_wb ),
|
|
.pc_wb_o ( pc_wb ),
|
|
|
|
.rf_waddr_id_i ( rf_waddr_id ),
|
|
.rf_wdata_id_i ( rf_wdata_id ),
|
|
.rf_we_id_i ( rf_we_id ),
|
|
|
|
.rf_wdata_lsu_i ( rf_wdata_lsu ),
|
|
.rf_we_lsu_i ( rf_we_lsu ),
|
|
|
|
.rf_wdata_fwd_wb_o ( rf_wdata_fwd_wb ),
|
|
|
|
.rf_waddr_wb_o ( rf_waddr_wb ),
|
|
.rf_wdata_wb_o ( rf_wdata_wb ),
|
|
.rf_we_wb_o ( rf_we_wb ),
|
|
|
|
.lsu_resp_valid_i ( lsu_resp_valid ),
|
|
|
|
.instr_done_wb_o ( instr_done_wb )
|
|
);
|
|
|
|
///////////////////////
|
|
// Register file ECC //
|
|
///////////////////////
|
|
|
|
logic [RegFileDataWidth-1:0] rf_wdata_wb_ecc;
|
|
logic [RegFileDataWidth-1:0] rf_rdata_a_ecc;
|
|
logic [RegFileDataWidth-1:0] rf_rdata_b_ecc;
|
|
logic rf_ecc_err_comb;
|
|
|
|
if (RegFileECC) begin : gen_regfile_ecc
|
|
|
|
logic [1:0] rf_ecc_err_a, rf_ecc_err_b;
|
|
logic rf_ecc_err_a_id, rf_ecc_err_b_id;
|
|
|
|
// ECC checkbit generation for regiter file wdata
|
|
prim_secded_39_32_enc regfile_ecc_enc (
|
|
.in (rf_wdata_wb),
|
|
.out (rf_wdata_wb_ecc)
|
|
);
|
|
|
|
// ECC checking on register file rdata
|
|
prim_secded_39_32_dec regfile_ecc_dec_a (
|
|
.in (rf_rdata_a_ecc),
|
|
.d_o (),
|
|
.syndrome_o (),
|
|
.err_o (rf_ecc_err_a)
|
|
);
|
|
prim_secded_39_32_dec regfile_ecc_dec_b (
|
|
.in (rf_rdata_b_ecc),
|
|
.d_o (),
|
|
.syndrome_o (),
|
|
.err_o (rf_ecc_err_b)
|
|
);
|
|
|
|
// Assign read outputs - no error correction, just trigger an alert
|
|
assign rf_rdata_a = rf_rdata_a_ecc[31:0];
|
|
assign rf_rdata_b = rf_rdata_b_ecc[31:0];
|
|
|
|
// Calculate errors - qualify with WB forwarding to avoid xprop into the alert signal
|
|
assign rf_ecc_err_a_id = |rf_ecc_err_a & rf_ren_a & ~rf_rd_a_wb_match;
|
|
assign rf_ecc_err_b_id = |rf_ecc_err_b & rf_ren_b & ~rf_rd_b_wb_match;
|
|
|
|
// Combined error
|
|
assign rf_ecc_err_comb = instr_valid_id & (rf_ecc_err_a_id | rf_ecc_err_b_id);
|
|
|
|
end else begin : gen_no_regfile_ecc
|
|
logic unused_rf_ren_a, unused_rf_ren_b;
|
|
logic unused_rf_rd_a_wb_match, unused_rf_rd_b_wb_match;
|
|
|
|
assign unused_rf_ren_a = rf_ren_a;
|
|
assign unused_rf_ren_b = rf_ren_b;
|
|
assign unused_rf_rd_a_wb_match = rf_rd_a_wb_match;
|
|
assign unused_rf_rd_b_wb_match = rf_rd_b_wb_match;
|
|
assign rf_wdata_wb_ecc = rf_wdata_wb;
|
|
assign rf_rdata_a = rf_rdata_a_ecc;
|
|
assign rf_rdata_b = rf_rdata_b_ecc;
|
|
assign rf_ecc_err_comb = 1'b0;
|
|
end
|
|
|
|
ibex_register_file #(
|
|
.RV32E (RV32E),
|
|
.DataWidth (RegFileDataWidth),
|
|
.DummyInstructions (DummyInstructions)
|
|
) register_file_i (
|
|
.clk_i ( clk_i ),
|
|
.rst_ni ( rst_ni ),
|
|
|
|
.test_en_i ( test_en_i ),
|
|
.dummy_instr_id_i ( dummy_instr_id ),
|
|
|
|
// Read port a
|
|
.raddr_a_i ( rf_raddr_a ),
|
|
.rdata_a_o ( rf_rdata_a_ecc ),
|
|
// Read port b
|
|
.raddr_b_i ( rf_raddr_b ),
|
|
.rdata_b_o ( rf_rdata_b_ecc ),
|
|
// write port
|
|
.waddr_a_i ( rf_waddr_wb ),
|
|
.wdata_a_i ( rf_wdata_wb_ecc ),
|
|
.we_a_i ( rf_we_wb )
|
|
);
|
|
|
|
///////////////////
|
|
// Alert outputs //
|
|
///////////////////
|
|
|
|
// Minor alert - core is in a recoverable state
|
|
// TODO add I$ ECC errors here
|
|
assign alert_minor_o = 1'b0;
|
|
|
|
// Major alert - core is unrecoverable
|
|
assign alert_major_o = rf_ecc_err_comb;
|
|
|
|
`ASSERT_KNOWN(IbexAlertMinorX, alert_minor_o)
|
|
`ASSERT_KNOWN(IbexAlertMajorX, alert_major_o)
|
|
|
|
// Explict INC_ASSERT block to avoid unused signal lint warnings were asserts are not included
|
|
`ifdef INC_ASSERT
|
|
// Signals used for assertions only
|
|
logic outstanding_load_resp;
|
|
logic outstanding_store_resp;
|
|
|
|
logic outstanding_load_id;
|
|
logic outstanding_store_id;
|
|
|
|
assign outstanding_load_id = id_stage_i.instr_executing & id_stage_i.lsu_req_dec &
|
|
~id_stage_i.lsu_we;
|
|
assign outstanding_store_id = id_stage_i.instr_executing & id_stage_i.lsu_req_dec &
|
|
id_stage_i.lsu_we;
|
|
|
|
if (WritebackStage) begin : gen_wb_stage
|
|
// When the writeback stage is present a load/store could be in ID or WB. A Load/store in ID can
|
|
// see a response before it moves to WB when it is unaligned otherwise we should only see
|
|
// a response when load/store is in WB.
|
|
assign outstanding_load_resp = outstanding_load_wb |
|
|
(outstanding_load_id & load_store_unit_i.split_misaligned_access);
|
|
|
|
assign outstanding_store_resp = outstanding_store_wb |
|
|
(outstanding_store_id & load_store_unit_i.split_misaligned_access);
|
|
|
|
// When writing back the result of a load, the load must have made it to writeback
|
|
`ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_wb, clk_i, !rst_ni)
|
|
end else begin : gen_no_wb_stage
|
|
// Without writeback stage only look into whether load or store is in ID to determine if
|
|
// a response is expected.
|
|
assign outstanding_load_resp = outstanding_load_id;
|
|
assign outstanding_store_resp = outstanding_store_id;
|
|
|
|
`ASSERT(NoMemRFWriteWithoutPendingLoad, rf_we_lsu |-> outstanding_load_id, clk_i, !rst_ni)
|
|
end
|
|
|
|
`ASSERT(NoMemResponseWithoutPendingAccess,
|
|
data_rvalid_i |-> outstanding_load_resp | outstanding_store_resp, clk_i, !rst_ni)
|
|
`endif
|
|
|
|
////////////////////////
|
|
// RF (Register File) //
|
|
////////////////////////
|
|
`ifdef RVFI
|
|
assign rvfi_rd_addr_wb = rf_waddr_wb;
|
|
assign rvfi_rd_wdata_wb = rf_we_wb ? rf_wdata_wb : rf_wdata_lsu;
|
|
assign rvfi_rd_we_wb = rf_we_wb | rf_we_lsu;
|
|
`endif
|
|
|
|
|
|
/////////////////////////////////////////
|
|
// CSRs (Control and Status Registers) //
|
|
/////////////////////////////////////////
|
|
|
|
assign csr_wdata = alu_operand_a_ex;
|
|
assign csr_addr = csr_num_e'(csr_access ? alu_operand_b_ex[11:0] : 12'b0);
|
|
|
|
ibex_cs_registers #(
|
|
.DbgTriggerEn ( DbgTriggerEn ),
|
|
.DataIndTiming ( DataIndTiming ),
|
|
.DummyInstructions ( DummyInstructions ),
|
|
.ICache ( ICache ),
|
|
.MHPMCounterNum ( MHPMCounterNum ),
|
|
.MHPMCounterWidth ( MHPMCounterWidth ),
|
|
.PMPEnable ( PMPEnable ),
|
|
.PMPGranularity ( PMPGranularity ),
|
|
.PMPNumRegions ( PMPNumRegions ),
|
|
.RV32E ( RV32E ),
|
|
.RV32M ( RV32M ),
|
|
.PointerAuthentication ( PointerAuthentication )
|
|
) cs_registers_i (
|
|
.clk_i ( clk ),
|
|
.rst_ni ( rst_ni ),
|
|
|
|
// Hart ID from outside
|
|
.hart_id_i ( hart_id_i ),
|
|
.priv_mode_id_o ( priv_mode_id ),
|
|
.priv_mode_if_o ( priv_mode_if ),
|
|
.priv_mode_lsu_o ( priv_mode_lsu ),
|
|
|
|
// mtvec
|
|
.csr_mtvec_o ( csr_mtvec ),
|
|
.csr_mtvec_init_i ( csr_mtvec_init ),
|
|
.boot_addr_i ( boot_addr_i ),
|
|
|
|
// Interface to CSRs ( SRAM like )
|
|
.csr_access_i ( csr_access ),
|
|
.csr_addr_i ( csr_addr ),
|
|
.csr_wdata_i ( csr_wdata ),
|
|
.csr_op_i ( csr_op ),
|
|
.csr_op_en_i ( csr_op_en ),
|
|
.csr_rdata_o ( csr_rdata ),
|
|
|
|
// Interrupt related control signals
|
|
.irq_software_i ( irq_software_i ),
|
|
.irq_timer_i ( irq_timer_i ),
|
|
.irq_external_i ( irq_external_i ),
|
|
.irq_fast_i ( irq_fast_i ),
|
|
.nmi_mode_i ( nmi_mode ),
|
|
.irq_pending_o ( irq_pending ),
|
|
.irqs_o ( irqs ),
|
|
.csr_mstatus_mie_o ( csr_mstatus_mie ),
|
|
.csr_mstatus_tw_o ( csr_mstatus_tw ),
|
|
.csr_mepc_o ( csr_mepc ),
|
|
|
|
// PMP
|
|
.csr_pmp_cfg_o ( csr_pmp_cfg ),
|
|
.csr_pmp_addr_o ( csr_pmp_addr ),
|
|
|
|
// Pointer Authenticaiton
|
|
.csr_pa_key_o ( csr_pa_key ),
|
|
|
|
// debug
|
|
.csr_depc_o ( csr_depc ),
|
|
.debug_mode_i ( debug_mode ),
|
|
.debug_cause_i ( debug_cause ),
|
|
.debug_csr_save_i ( debug_csr_save ),
|
|
.debug_single_step_o ( debug_single_step ),
|
|
.debug_ebreakm_o ( debug_ebreakm ),
|
|
.debug_ebreaku_o ( debug_ebreaku ),
|
|
.trigger_match_o ( trigger_match ),
|
|
|
|
.pc_if_i ( pc_if ),
|
|
.pc_id_i ( pc_id ),
|
|
.pc_wb_i ( pc_wb ),
|
|
|
|
.data_ind_timing_o ( data_ind_timing ),
|
|
.dummy_instr_en_o ( dummy_instr_en ),
|
|
.dummy_instr_mask_o ( dummy_instr_mask ),
|
|
.dummy_instr_seed_en_o ( dummy_instr_seed_en ),
|
|
.dummy_instr_seed_o ( dummy_instr_seed ),
|
|
.icache_enable_o ( icache_enable ),
|
|
|
|
.csr_save_if_i ( csr_save_if ),
|
|
.csr_save_id_i ( csr_save_id ),
|
|
.csr_save_wb_i ( csr_save_wb ),
|
|
.csr_restore_mret_i ( csr_restore_mret_id ),
|
|
.csr_restore_dret_i ( csr_restore_dret_id ),
|
|
.csr_save_cause_i ( csr_save_cause ),
|
|
.csr_mcause_i ( exc_cause ),
|
|
.csr_mtval_i ( csr_mtval ),
|
|
.illegal_csr_insn_o ( illegal_csr_insn_id ),
|
|
|
|
// performance counter related signals
|
|
.instr_ret_i ( instr_id_done ),
|
|
.instr_ret_compressed_i ( instr_id_done_compressed ),
|
|
.iside_wait_i ( perf_iside_wait ),
|
|
.jump_i ( perf_jump ),
|
|
.branch_i ( perf_branch ),
|
|
.branch_taken_i ( perf_tbranch ),
|
|
.mem_load_i ( perf_load ),
|
|
.mem_store_i ( perf_store ),
|
|
.dside_wait_i ( perf_dside_wait ),
|
|
.mul_wait_i ( perf_mul_wait ),
|
|
.div_wait_i ( perf_div_wait ),
|
|
.pac_i ( perf_pac ),
|
|
.aut_i ( perf_aut )
|
|
);
|
|
|
|
// These assertions are in top-level as instr_valid_id required as the enable term
|
|
`ASSERT(IbexCsrOpValid, instr_valid_id |-> csr_op inside {
|
|
CSR_OP_READ,
|
|
CSR_OP_WRITE,
|
|
CSR_OP_SET,
|
|
CSR_OP_CLEAR
|
|
})
|
|
`ASSERT_KNOWN_IF(IbexCsrWdataIntKnown, cs_registers_i.csr_wdata_int, csr_op_en)
|
|
|
|
if (PMPEnable) begin : g_pmp
|
|
logic [33:0] pmp_req_addr [PMP_NUM_CHAN];
|
|
pmp_req_e pmp_req_type [PMP_NUM_CHAN];
|
|
priv_lvl_e pmp_priv_lvl [PMP_NUM_CHAN];
|
|
|
|
assign pmp_req_addr[PMP_I] = {2'b00,instr_addr_o[31:0]};
|
|
assign pmp_req_type[PMP_I] = PMP_ACC_EXEC;
|
|
assign pmp_priv_lvl[PMP_I] = priv_mode_if;
|
|
assign pmp_req_addr[PMP_D] = {2'b00,data_addr_o[31:0]};
|
|
assign pmp_req_type[PMP_D] = data_we_o ? PMP_ACC_WRITE : PMP_ACC_READ;
|
|
assign pmp_priv_lvl[PMP_D] = priv_mode_lsu;
|
|
|
|
ibex_pmp #(
|
|
.PMPGranularity ( PMPGranularity ),
|
|
.PMPNumChan ( PMP_NUM_CHAN ),
|
|
.PMPNumRegions ( PMPNumRegions )
|
|
) pmp_i (
|
|
.clk_i ( clk ),
|
|
.rst_ni ( rst_ni ),
|
|
// Interface to CSRs
|
|
.csr_pmp_cfg_i ( csr_pmp_cfg ),
|
|
.csr_pmp_addr_i ( csr_pmp_addr ),
|
|
.priv_mode_i ( pmp_priv_lvl ),
|
|
// Access checking channels
|
|
.pmp_req_addr_i ( pmp_req_addr ),
|
|
.pmp_req_type_i ( pmp_req_type ),
|
|
.pmp_req_err_o ( pmp_req_err )
|
|
);
|
|
end else begin : g_no_pmp
|
|
// Unused signal tieoff
|
|
priv_lvl_e unused_priv_lvl_if, unused_priv_lvl_ls;
|
|
logic [33:0] unused_csr_pmp_addr [PMPNumRegions];
|
|
pmp_cfg_t unused_csr_pmp_cfg [PMPNumRegions];
|
|
assign unused_priv_lvl_if = priv_mode_if;
|
|
assign unused_priv_lvl_ls = priv_mode_lsu;
|
|
assign unused_csr_pmp_addr = csr_pmp_addr;
|
|
assign unused_csr_pmp_cfg = csr_pmp_cfg;
|
|
|
|
// Output tieoff
|
|
assign pmp_req_err[PMP_I] = 1'b0;
|
|
assign pmp_req_err[PMP_D] = 1'b0;
|
|
end
|
|
|
|
`ifdef RVFI
|
|
// When writeback stage is present RVFI information is emitted when instruction is finished in
|
|
// third stage but some information must be captured whilst the instruction is in the second
|
|
// stage. Without writeback stage RVFI information is all emitted when instruction retires in
|
|
// second stage. RVFI outputs are all straight from flops. So 2 stage pipeline requires a single
|
|
// set of flops (instr_info => RVFI_out), 3 stage pipeline requires two sets (instr_info => wb
|
|
// => RVFI_out)
|
|
localparam int RVFI_STAGES = WritebackStage ? 2 : 1;
|
|
|
|
logic rvfi_stage_valid [RVFI_STAGES];
|
|
logic [63:0] rvfi_stage_order [RVFI_STAGES];
|
|
logic [31:0] rvfi_stage_insn [RVFI_STAGES];
|
|
logic rvfi_stage_trap [RVFI_STAGES];
|
|
logic rvfi_stage_halt [RVFI_STAGES];
|
|
logic rvfi_stage_intr [RVFI_STAGES];
|
|
logic [ 1:0] rvfi_stage_mode [RVFI_STAGES];
|
|
logic [ 1:0] rvfi_stage_ixl [RVFI_STAGES];
|
|
logic [ 4:0] rvfi_stage_rs1_addr [RVFI_STAGES];
|
|
logic [ 4:0] rvfi_stage_rs2_addr [RVFI_STAGES];
|
|
logic [ 4:0] rvfi_stage_rs3_addr [RVFI_STAGES];
|
|
logic [31:0] rvfi_stage_rs1_rdata [RVFI_STAGES];
|
|
logic [31:0] rvfi_stage_rs2_rdata [RVFI_STAGES];
|
|
logic [31:0] rvfi_stage_rs3_rdata [RVFI_STAGES];
|
|
logic [ 4:0] rvfi_stage_rd_addr [RVFI_STAGES];
|
|
logic [31:0] rvfi_stage_rd_wdata [RVFI_STAGES];
|
|
logic [31:0] rvfi_stage_pc_rdata [RVFI_STAGES];
|
|
logic [31:0] rvfi_stage_pc_wdata [RVFI_STAGES];
|
|
logic [31:0] rvfi_stage_mem_addr [RVFI_STAGES];
|
|
logic [ 3:0] rvfi_stage_mem_rmask [RVFI_STAGES];
|
|
logic [ 3:0] rvfi_stage_mem_wmask [RVFI_STAGES];
|
|
logic [31:0] rvfi_stage_mem_rdata [RVFI_STAGES];
|
|
logic [31:0] rvfi_stage_mem_wdata [RVFI_STAGES];
|
|
|
|
logic rvfi_stage_valid_d [RVFI_STAGES];
|
|
|
|
assign rvfi_valid = rvfi_stage_valid [RVFI_STAGES-1];
|
|
assign rvfi_order = rvfi_stage_order [RVFI_STAGES-1];
|
|
assign rvfi_insn = rvfi_stage_insn [RVFI_STAGES-1];
|
|
assign rvfi_trap = rvfi_stage_trap [RVFI_STAGES-1];
|
|
assign rvfi_halt = rvfi_stage_halt [RVFI_STAGES-1];
|
|
assign rvfi_intr = rvfi_stage_intr [RVFI_STAGES-1];
|
|
assign rvfi_mode = rvfi_stage_mode [RVFI_STAGES-1];
|
|
assign rvfi_ixl = rvfi_stage_ixl [RVFI_STAGES-1];
|
|
assign rvfi_rs1_addr = rvfi_stage_rs1_addr [RVFI_STAGES-1];
|
|
assign rvfi_rs2_addr = rvfi_stage_rs2_addr [RVFI_STAGES-1];
|
|
assign rvfi_rs3_addr = rvfi_stage_rs3_addr [RVFI_STAGES-1];
|
|
assign rvfi_rs1_rdata = rvfi_stage_rs1_rdata[RVFI_STAGES-1];
|
|
assign rvfi_rs2_rdata = rvfi_stage_rs2_rdata[RVFI_STAGES-1];
|
|
assign rvfi_rs3_rdata = rvfi_stage_rs3_rdata[RVFI_STAGES-1];
|
|
assign rvfi_rd_addr = rvfi_stage_rd_addr [RVFI_STAGES-1];
|
|
assign rvfi_rd_wdata = rvfi_stage_rd_wdata [RVFI_STAGES-1];
|
|
assign rvfi_pc_rdata = rvfi_stage_pc_rdata [RVFI_STAGES-1];
|
|
assign rvfi_pc_wdata = rvfi_stage_pc_wdata [RVFI_STAGES-1];
|
|
assign rvfi_mem_addr = rvfi_stage_mem_addr [RVFI_STAGES-1];
|
|
assign rvfi_mem_rmask = rvfi_stage_mem_rmask[RVFI_STAGES-1];
|
|
assign rvfi_mem_wmask = rvfi_stage_mem_wmask[RVFI_STAGES-1];
|
|
assign rvfi_mem_rdata = rvfi_stage_mem_rdata[RVFI_STAGES-1];
|
|
assign rvfi_mem_wdata = rvfi_stage_mem_wdata[RVFI_STAGES-1];
|
|
|
|
if (WritebackStage) begin : gen_rvfi_wb_stage
|
|
logic unused_instr_new_id;
|
|
|
|
assign unused_instr_new_id = instr_new_id;
|
|
|
|
// With writeback stage first RVFI stage buffers instruction information captured in ID/EX
|
|
// awaiting instruction retirement and RF Write data/Mem read data whilst instruction is in WB
|
|
// So first stage becomes valid when instruction leaves ID/EX stage and remains valid until
|
|
// instruction leaves WB
|
|
assign rvfi_stage_valid_d[0] = (instr_id_done & ~dummy_instr_id) |
|
|
(rvfi_stage_valid[0] & ~instr_done_wb);
|
|
// Second stage is output stage so simple valid cycle after instruction leaves WB (and so has
|
|
// retired)
|
|
assign rvfi_stage_valid_d[1] = instr_done_wb;
|
|
|
|
// Signal new instruction in WB cycle after instruction leaves ID/EX (to enter WB)
|
|
logic rvfi_instr_new_wb_q;
|
|
|
|
assign rvfi_instr_new_wb = rvfi_instr_new_wb_q;
|
|
|
|
always_ff @(posedge clk or negedge rst_ni) begin
|
|
if (~rst_ni) begin
|
|
rvfi_instr_new_wb_q <= 0;
|
|
end else begin
|
|
rvfi_instr_new_wb_q <= instr_id_done;
|
|
end
|
|
end
|
|
end else begin : gen_rvfi_no_wb_stage
|
|
// Without writeback stage first RVFI stage is output stage so simply valid the cycle after
|
|
// instruction leaves ID/EX (and so has retired)
|
|
assign rvfi_stage_valid_d[0] = instr_id_done & ~dummy_instr_id;
|
|
// Without writeback stage signal new instr_new_wb when instruction enters ID/EX to correctly
|
|
// setup register write signals
|
|
assign rvfi_instr_new_wb = instr_new_id;
|
|
end
|
|
|
|
for (genvar i = 0;i < RVFI_STAGES; i = i + 1) begin : g_rvfi_stages
|
|
always_ff @(posedge clk or negedge rst_ni) begin
|
|
if (!rst_ni) begin
|
|
rvfi_stage_halt[i] <= '0;
|
|
rvfi_stage_trap[i] <= '0;
|
|
rvfi_stage_intr[i] <= '0;
|
|
rvfi_stage_order[i] <= '0;
|
|
rvfi_stage_insn[i] <= '0;
|
|
rvfi_stage_mode[i] <= {PRIV_LVL_M};
|
|
rvfi_stage_ixl[i] <= CSR_MISA_MXL;
|
|
rvfi_stage_rs1_addr[i] <= '0;
|
|
rvfi_stage_rs2_addr[i] <= '0;
|
|
rvfi_stage_rs3_addr[i] <= '0;
|
|
rvfi_stage_pc_rdata[i] <= '0;
|
|
rvfi_stage_pc_wdata[i] <= '0;
|
|
rvfi_stage_mem_rmask[i] <= '0;
|
|
rvfi_stage_mem_wmask[i] <= '0;
|
|
rvfi_stage_valid[i] <= '0;
|
|
rvfi_stage_rs1_rdata[i] <= '0;
|
|
rvfi_stage_rs2_rdata[i] <= '0;
|
|
rvfi_stage_rs3_rdata[i] <= '0;
|
|
rvfi_stage_rd_wdata[i] <= '0;
|
|
rvfi_stage_rd_addr[i] <= '0;
|
|
rvfi_stage_mem_rdata[i] <= '0;
|
|
rvfi_stage_mem_wdata[i] <= '0;
|
|
rvfi_stage_mem_addr[i] <= '0;
|
|
end else begin
|
|
rvfi_stage_valid[i] <= rvfi_stage_valid_d[i];
|
|
|
|
if (i == 0) begin
|
|
if(instr_id_done) begin
|
|
rvfi_stage_halt[i] <= '0;
|
|
rvfi_stage_trap[i] <= illegal_insn_id;
|
|
rvfi_stage_intr[i] <= rvfi_intr_d;
|
|
rvfi_stage_order[i] <= rvfi_stage_order[i] + 64'(rvfi_stage_valid_d[i]);
|
|
rvfi_stage_insn[i] <= rvfi_insn_id;
|
|
rvfi_stage_mode[i] <= {priv_mode_id};
|
|
rvfi_stage_ixl[i] <= CSR_MISA_MXL;
|
|
rvfi_stage_rs1_addr[i] <= rvfi_rs1_addr_d;
|
|
rvfi_stage_rs2_addr[i] <= rvfi_rs2_addr_d;
|
|
rvfi_stage_rs3_addr[i] <= rvfi_rs3_addr_d;
|
|
rvfi_stage_pc_rdata[i] <= pc_id;
|
|
rvfi_stage_pc_wdata[i] <= pc_set ? branch_target_ex : pc_if;
|
|
rvfi_stage_mem_rmask[i] <= rvfi_mem_mask_int;
|
|
rvfi_stage_mem_wmask[i] <= data_we_o ? rvfi_mem_mask_int : 4'b0000;
|
|
rvfi_stage_rs1_rdata[i] <= rvfi_rs1_data_d;
|
|
rvfi_stage_rs2_rdata[i] <= rvfi_rs2_data_d;
|
|
rvfi_stage_rs3_rdata[i] <= rvfi_rs3_data_d;
|
|
rvfi_stage_rd_addr[i] <= rvfi_rd_addr_d;
|
|
rvfi_stage_rd_wdata[i] <= rvfi_rd_wdata_d;
|
|
rvfi_stage_mem_rdata[i] <= rvfi_mem_rdata_d;
|
|
rvfi_stage_mem_wdata[i] <= rvfi_mem_wdata_d;
|
|
rvfi_stage_mem_addr[i] <= rvfi_mem_addr_d;
|
|
end
|
|
end else begin
|
|
if(instr_done_wb) begin
|
|
rvfi_stage_halt[i] <= rvfi_stage_halt[i-1];
|
|
rvfi_stage_trap[i] <= rvfi_stage_trap[i-1];
|
|
rvfi_stage_intr[i] <= rvfi_stage_intr[i-1];
|
|
rvfi_stage_order[i] <= rvfi_stage_order[i-1];
|
|
rvfi_stage_insn[i] <= rvfi_stage_insn[i-1];
|
|
rvfi_stage_mode[i] <= rvfi_stage_mode[i-1];
|
|
rvfi_stage_ixl[i] <= rvfi_stage_ixl[i-1];
|
|
rvfi_stage_rs1_addr[i] <= rvfi_stage_rs1_addr[i-1];
|
|
rvfi_stage_rs2_addr[i] <= rvfi_stage_rs2_addr[i-1];
|
|
rvfi_stage_rs3_addr[i] <= rvfi_stage_rs3_addr[i-1];
|
|
rvfi_stage_pc_rdata[i] <= rvfi_stage_pc_rdata[i-1];
|
|
rvfi_stage_pc_wdata[i] <= rvfi_stage_pc_wdata[i-1];
|
|
rvfi_stage_mem_rmask[i] <= rvfi_stage_mem_rmask[i-1];
|
|
rvfi_stage_mem_wmask[i] <= rvfi_stage_mem_wmask[i-1];
|
|
rvfi_stage_rs1_rdata[i] <= rvfi_stage_rs1_rdata[i-1];
|
|
rvfi_stage_rs2_rdata[i] <= rvfi_stage_rs2_rdata[i-1];
|
|
rvfi_stage_rs3_rdata[i] <= rvfi_stage_rs3_rdata[i-1];
|
|
rvfi_stage_mem_wdata[i] <= rvfi_stage_mem_wdata[i-1];
|
|
rvfi_stage_mem_addr[i] <= rvfi_stage_mem_addr[i-1];
|
|
|
|
// For 2 RVFI_STAGES/Writeback Stage ignore first stage flops for rd_addr, rd_wdata and
|
|
// mem_rdata. For RF write addr/data actual write happens in writeback so capture
|
|
// address/data there. For mem_rdata that is only available from the writeback stage.
|
|
// Previous stage flops still exist in RTL as they are used by the non writeback config
|
|
rvfi_stage_rd_addr[i] <= rvfi_rd_addr_d;
|
|
rvfi_stage_rd_wdata[i] <= rvfi_rd_wdata_d;
|
|
rvfi_stage_mem_rdata[i] <= rvfi_mem_rdata_d;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
// Memory adddress/write data available first cycle of ld/st instruction from register read
|
|
always_comb begin
|
|
if (instr_first_cycle_id) begin
|
|
rvfi_mem_addr_d = alu_adder_result_ex;
|
|
rvfi_mem_wdata_d = lsu_wdata;
|
|
end else begin
|
|
rvfi_mem_addr_d = rvfi_mem_addr_q;
|
|
rvfi_mem_wdata_d = rvfi_mem_wdata_q;
|
|
end
|
|
end
|
|
|
|
// Capture read data from LSU when it becomes valid
|
|
always_comb begin
|
|
if (lsu_resp_valid) begin
|
|
rvfi_mem_rdata_d = rf_wdata_lsu;
|
|
end else begin
|
|
rvfi_mem_rdata_d = rvfi_mem_rdata_q;
|
|
end
|
|
end
|
|
|
|
always_ff @(posedge clk or negedge rst_ni) begin
|
|
if (!rst_ni) begin
|
|
rvfi_mem_addr_q <= '0;
|
|
rvfi_mem_rdata_q <= '0;
|
|
rvfi_mem_wdata_q <= '0;
|
|
end else begin
|
|
rvfi_mem_addr_q <= rvfi_mem_addr_d;
|
|
rvfi_mem_rdata_q <= rvfi_mem_rdata_d;
|
|
rvfi_mem_wdata_q <= rvfi_mem_wdata_d;
|
|
end
|
|
end
|
|
// Byte enable based on data type
|
|
always_comb begin
|
|
unique case (lsu_type)
|
|
2'b00: rvfi_mem_mask_int = 4'b1111;
|
|
2'b01: rvfi_mem_mask_int = 4'b0011;
|
|
2'b10: rvfi_mem_mask_int = 4'b0001;
|
|
default: rvfi_mem_mask_int = 4'b0000;
|
|
endcase
|
|
end
|
|
|
|
always_comb begin
|
|
if (instr_is_compressed_id) begin
|
|
rvfi_insn_id = {16'b0, instr_rdata_c_id};
|
|
end else begin
|
|
rvfi_insn_id = instr_rdata_id;
|
|
end
|
|
end
|
|
|
|
// Source registers 1 and 2 are read in the first instruction cycle
|
|
// Source register 3 is read in the second instruction cycle.
|
|
always_comb begin
|
|
if (instr_first_cycle_id) begin
|
|
rvfi_rs1_data_d = rf_ren_a ? multdiv_operand_a_ex : '0;
|
|
rvfi_rs1_addr_d = rf_ren_a ? rf_raddr_a : '0;
|
|
rvfi_rs2_data_d = rf_ren_b ? multdiv_operand_b_ex : '0;
|
|
rvfi_rs2_addr_d = rf_ren_b ? rf_raddr_b : '0;
|
|
rvfi_rs3_data_d = '0;
|
|
rvfi_rs3_addr_d = '0;
|
|
end else begin
|
|
rvfi_rs1_data_d = rvfi_rs1_data_q;
|
|
rvfi_rs1_addr_d = rvfi_rs1_addr_q;
|
|
rvfi_rs2_data_d = rvfi_rs2_data_q;
|
|
rvfi_rs2_addr_d = rvfi_rs2_addr_q;
|
|
rvfi_rs3_data_d = multdiv_operand_a_ex;
|
|
rvfi_rs3_addr_d = rf_raddr_a;
|
|
end
|
|
end
|
|
always_ff @(posedge clk or negedge rst_ni) begin
|
|
if (!rst_ni) begin
|
|
rvfi_rs1_data_q <= '0;
|
|
rvfi_rs1_addr_q <= '0;
|
|
rvfi_rs2_data_q <= '0;
|
|
rvfi_rs2_addr_q <= '0;
|
|
|
|
end else begin
|
|
rvfi_rs1_data_q <= rvfi_rs1_data_d;
|
|
rvfi_rs1_addr_q <= rvfi_rs1_addr_d;
|
|
rvfi_rs2_data_q <= rvfi_rs2_data_d;
|
|
rvfi_rs2_addr_q <= rvfi_rs2_addr_d;
|
|
end
|
|
end
|
|
|
|
always_comb begin
|
|
if(rvfi_rd_we_wb) begin
|
|
// Capture address/data of write to register file
|
|
rvfi_rd_addr_d = rvfi_rd_addr_wb;
|
|
// If writing to x0 zero write data as required by RVFI specification
|
|
if(rvfi_rd_addr_wb == 5'b0) begin
|
|
rvfi_rd_wdata_d = '0;
|
|
end else begin
|
|
rvfi_rd_wdata_d = rvfi_rd_wdata_wb;
|
|
end
|
|
end else if(rvfi_instr_new_wb) begin
|
|
// If no RF write but new instruction in Writeback (when present) or ID/EX (when no writeback
|
|
// stage present) then zero RF write address/data as required by RVFI specification
|
|
rvfi_rd_addr_d = '0;
|
|
rvfi_rd_wdata_d = '0;
|
|
end else begin
|
|
// Otherwise maintain previous value
|
|
rvfi_rd_addr_d = rvfi_rd_addr_q;
|
|
rvfi_rd_wdata_d = rvfi_rd_wdata_q;
|
|
end
|
|
end
|
|
|
|
// RD write register is refreshed only once per cycle and
|
|
// then it is kept stable for the cycle.
|
|
always_ff @(posedge clk or negedge rst_ni) begin
|
|
if (!rst_ni) begin
|
|
rvfi_rd_addr_q <= '0;
|
|
rvfi_rd_wdata_q <= '0;
|
|
end else begin
|
|
rvfi_rd_addr_q <= rvfi_rd_addr_d;
|
|
rvfi_rd_wdata_q <= rvfi_rd_wdata_d;
|
|
end
|
|
end
|
|
|
|
// rvfi_intr must be set for first instruction that is part of a trap handler.
|
|
// On the first cycle of a new instruction see if a trap PC was set by the previous instruction,
|
|
// otherwise maintain value.
|
|
assign rvfi_intr_d = instr_first_cycle_id ? rvfi_set_trap_pc_q : rvfi_intr_q;
|
|
|
|
always_comb begin
|
|
rvfi_set_trap_pc_d = rvfi_set_trap_pc_q;
|
|
|
|
if (pc_set && pc_mux_id == PC_EXC &&
|
|
(exc_pc_mux_id == EXC_PC_EXC || exc_pc_mux_id == EXC_PC_IRQ)) begin
|
|
// PC is set to enter a trap handler
|
|
rvfi_set_trap_pc_d = 1'b1;
|
|
end else if (rvfi_set_trap_pc_q && instr_id_done) begin
|
|
// first instruction has been executed after PC is set to trap handler
|
|
rvfi_set_trap_pc_d = 1'b0;
|
|
end
|
|
end
|
|
|
|
always_ff @(posedge clk or negedge rst_ni) begin
|
|
if (!rst_ni) begin
|
|
rvfi_set_trap_pc_q <= 1'b0;
|
|
rvfi_intr_q <= 1'b0;
|
|
end else begin
|
|
rvfi_set_trap_pc_q <= rvfi_set_trap_pc_d;
|
|
rvfi_intr_q <= rvfi_intr_d;
|
|
end
|
|
end
|
|
|
|
`endif
|
|
|
|
if (PointerAuthentication) begin : g_pa
|
|
ibex_pointer_authentication pointer_authentication_i (
|
|
.clk_i ( clk ),
|
|
.rst_ni ( rst_ni ),
|
|
.csr_pa_key_i ( csr_pa_key ),
|
|
.pac_en_i ( pa_pac_en ),
|
|
.aut_en_i ( pa_aut_en ),
|
|
.pa_data0_i ( pa_data0 ),
|
|
.pa_data1_i ( pa_data1 ),
|
|
.pa_ready_id_i ( pa_ready_id ),
|
|
.pa_result_o ( pa_result ),
|
|
.pa_valid_o ( pa_valid )
|
|
);
|
|
end else begin : g_no_pa
|
|
logic unused_pa_pac_en;
|
|
logic unused_pa_aut_en;
|
|
logic [31:0] unused_pa_data0;
|
|
logic [31:0] unused_pa_data1;
|
|
logic unused_pa_ready_id;
|
|
logic [127:0] unused_csr_pa_key;
|
|
assign unused_pa_pac_en = pa_pac_en;
|
|
assign unused_pa_aut_en = pa_aut_en;
|
|
assign unused_pa_data0 = pa_data0;
|
|
assign unused_pa_data1 = pa_data1;
|
|
assign unused_pa_ready_id = pa_ready_id;
|
|
assign unused_csr_pa_key = csr_pa_key;
|
|
|
|
// Output tieoff
|
|
assign pa_result = '0;
|
|
assign pa_valid = '0;
|
|
end
|
|
|
|
endmodule
|