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1aa4d5a32b
This commit contains some final optimizations regarding the bit
manipulation extension as well as the parametrization into a balanced
version and a full performance version.
Balanced Version:
* Supports ZBB, ZBS, ZBF and ZBT extensions
* Dual cycle instructions:
ror[i], rol, cmov, cmix fsl, fsr[i]
* Everything else completes in a single cycle.
Full Version:
* Supports all 32b sub extensions.
* Dual cycle instructions:
ror[i], rol, cmov, cmix fsl, fsr[i], crc32[c], bext, bdep
* Everything else completes in a single cycle.
Notable Changes:
* bext/bdep are now multi-cycle: Sharing additional register
with multiplier module
* grev/gorc instructions are implemented in separate structures
rather than sharing the shifter or butterfly network.
* Speed up decision on using rs1 or rs3 for alu_operand_a by
introducing single-bit register, to identify ternary
instructions in their first cycle.
* Introduce enumerated parameter to chose bit manipulation
implementation
Signed-off-by: ganoam <gnoam@live.com>
227 lines
9.6 KiB
Systemverilog
227 lines
9.6 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Execution stage
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*
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* Execution block: Hosts ALU and MUL/DIV unit
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*/
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module ibex_ex_block #(
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parameter bit RV32M = 1,
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parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone,
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parameter bit BranchTargetALU = 0,
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parameter MultiplierImplementation = "fast"
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) (
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input logic clk_i,
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input logic rst_ni,
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// ALU
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input ibex_pkg::alu_op_e alu_operator_i,
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input logic [31:0] alu_operand_a_i,
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input logic [31:0] alu_operand_b_i,
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input logic alu_instr_first_cycle_i,
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// Branch Target ALU
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// All of these signals are unusued when BranchTargetALU == 0
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input logic [31:0] bt_a_operand_i,
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input logic [31:0] bt_b_operand_i,
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// Multiplier/Divider
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input ibex_pkg::md_op_e multdiv_operator_i,
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input logic mult_en_i, // dynamic enable signal, for FSM control
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input logic div_en_i, // dynamic enable signal, for FSM control
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input logic mult_sel_i, // static decoder output, for data muxes
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input logic div_sel_i, // static decoder output, for data muxes
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input logic [1:0] multdiv_signed_mode_i,
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input logic [31:0] multdiv_operand_a_i,
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input logic [31:0] multdiv_operand_b_i,
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input logic multdiv_ready_id_i,
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input logic data_ind_timing_i,
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// intermediate val reg
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output logic [1:0] imd_val_we_o,
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output logic [33:0] imd_val_d_o[2],
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input logic [33:0] imd_val_q_i[2],
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// Outputs
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output logic [31:0] alu_adder_result_ex_o, // to LSU
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output logic [31:0] result_ex_o,
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output logic [31:0] branch_target_o, // to IF
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output logic branch_decision_o, // to ID
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output logic ex_valid_o // EX has valid output
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);
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import ibex_pkg::*;
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logic [31:0] alu_result, multdiv_result;
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logic [32:0] multdiv_alu_operand_b, multdiv_alu_operand_a;
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logic [33:0] alu_adder_result_ext;
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logic alu_cmp_result, alu_is_equal_result;
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logic multdiv_valid;
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logic multdiv_sel;
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logic [31:0] alu_imd_val_q[2];
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logic [31:0] alu_imd_val_d[2];
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logic [ 1:0] alu_imd_val_we;
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logic [33:0] multdiv_imd_val_d[2];
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logic [ 1:0] multdiv_imd_val_we;
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/*
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The multdiv_i output is never selected if RV32M=0
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At synthesis time, all the combinational and sequential logic
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from the multdiv_i module are eliminated
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*/
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if (RV32M) begin : gen_multdiv_m
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assign multdiv_sel = mult_sel_i | div_sel_i;
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end else begin : gen_multdiv_no_m
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assign multdiv_sel = 1'b0;
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end
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// Intermediate Value Register Mux
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assign imd_val_d_o[0] = multdiv_sel ? multdiv_imd_val_d[0] : {2'b0, alu_imd_val_d[0]};
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assign imd_val_d_o[1] = multdiv_sel ? multdiv_imd_val_d[1] : {2'b0, alu_imd_val_d[1]};
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assign imd_val_we_o = multdiv_sel ? multdiv_imd_val_we : alu_imd_val_we;
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assign alu_imd_val_q = '{imd_val_q_i[0][31:0], imd_val_q_i[1][31:0]};
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assign result_ex_o = multdiv_sel ? multdiv_result : alu_result;
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// branch handling
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assign branch_decision_o = alu_cmp_result;
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if (BranchTargetALU) begin : g_branch_target_alu
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logic [32:0] bt_alu_result;
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logic unused_bt_carry;
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assign bt_alu_result = bt_a_operand_i + bt_b_operand_i;
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assign unused_bt_carry = bt_alu_result[32];
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assign branch_target_o = bt_alu_result[31:0];
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end else begin : g_no_branch_target_alu
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// Unused bt_operand signals cause lint errors, this avoids them
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logic [31:0] unused_bt_a_operand, unused_bt_b_operand;
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assign unused_bt_a_operand = bt_a_operand_i;
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assign unused_bt_b_operand = bt_b_operand_i;
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assign branch_target_o = alu_adder_result_ex_o;
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end
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/////////
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// ALU //
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/////////
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ibex_alu #(
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.RV32B(RV32B)
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) alu_i (
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.operator_i ( alu_operator_i ),
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.operand_a_i ( alu_operand_a_i ),
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.operand_b_i ( alu_operand_b_i ),
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.instr_first_cycle_i ( alu_instr_first_cycle_i ),
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.imd_val_q_i ( alu_imd_val_q ),
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.imd_val_we_o ( alu_imd_val_we ),
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.imd_val_d_o ( alu_imd_val_d ),
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.multdiv_operand_a_i ( multdiv_alu_operand_a ),
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.multdiv_operand_b_i ( multdiv_alu_operand_b ),
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.multdiv_sel_i ( multdiv_sel ),
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.adder_result_o ( alu_adder_result_ex_o ),
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.adder_result_ext_o ( alu_adder_result_ext ),
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.result_o ( alu_result ),
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.comparison_result_o ( alu_cmp_result ),
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.is_equal_result_o ( alu_is_equal_result )
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);
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////////////////
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// Multiplier //
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////////////////
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if (MultiplierImplementation == "slow") begin : gen_multdiv_slow
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ibex_multdiv_slow multdiv_i (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.mult_en_i ( mult_en_i ),
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.div_en_i ( div_en_i ),
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.mult_sel_i ( mult_sel_i ),
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.div_sel_i ( div_sel_i ),
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.operator_i ( multdiv_operator_i ),
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.signed_mode_i ( multdiv_signed_mode_i ),
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.op_a_i ( multdiv_operand_a_i ),
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.op_b_i ( multdiv_operand_b_i ),
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.alu_adder_ext_i ( alu_adder_result_ext ),
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.alu_adder_i ( alu_adder_result_ex_o ),
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.equal_to_zero_i ( alu_is_equal_result ),
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.data_ind_timing_i ( data_ind_timing_i ),
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.valid_o ( multdiv_valid ),
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.alu_operand_a_o ( multdiv_alu_operand_a ),
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.alu_operand_b_o ( multdiv_alu_operand_b ),
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.imd_val_q_i ( imd_val_q_i ),
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.imd_val_d_o ( multdiv_imd_val_d ),
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.imd_val_we_o ( multdiv_imd_val_we ),
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.multdiv_ready_id_i ( multdiv_ready_id_i ),
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.multdiv_result_o ( multdiv_result )
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);
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end else if (MultiplierImplementation == "fast") begin : gen_multdiv_fast
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ibex_multdiv_fast # (
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.SingleCycleMultiply (0)
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) multdiv_i (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.mult_en_i ( mult_en_i ),
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.div_en_i ( div_en_i ),
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.mult_sel_i ( mult_sel_i ),
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.div_sel_i ( div_sel_i ),
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.operator_i ( multdiv_operator_i ),
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.signed_mode_i ( multdiv_signed_mode_i ),
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.op_a_i ( multdiv_operand_a_i ),
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.op_b_i ( multdiv_operand_b_i ),
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.alu_operand_a_o ( multdiv_alu_operand_a ),
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.alu_operand_b_o ( multdiv_alu_operand_b ),
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.alu_adder_ext_i ( alu_adder_result_ext ),
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.alu_adder_i ( alu_adder_result_ex_o ),
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.equal_to_zero_i ( alu_is_equal_result ),
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.data_ind_timing_i ( data_ind_timing_i ),
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.imd_val_q_i ( imd_val_q_i ),
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.imd_val_d_o ( multdiv_imd_val_d ),
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.imd_val_we_o ( multdiv_imd_val_we ),
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.multdiv_ready_id_i ( multdiv_ready_id_i ),
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.valid_o ( multdiv_valid ),
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.multdiv_result_o ( multdiv_result )
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);
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end else if (MultiplierImplementation == "single-cycle") begin: gen_multdiv_single_cycle
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ibex_multdiv_fast #(
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.SingleCycleMultiply(1)
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) multdiv_i (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.mult_en_i ( mult_en_i ),
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.div_en_i ( div_en_i ),
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.mult_sel_i ( mult_sel_i ),
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.div_sel_i ( div_sel_i ),
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.operator_i ( multdiv_operator_i ),
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.signed_mode_i ( multdiv_signed_mode_i ),
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.op_a_i ( multdiv_operand_a_i ),
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.op_b_i ( multdiv_operand_b_i ),
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.alu_operand_a_o ( multdiv_alu_operand_a ),
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.alu_operand_b_o ( multdiv_alu_operand_b ),
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.alu_adder_ext_i ( alu_adder_result_ext ),
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.alu_adder_i ( alu_adder_result_ex_o ),
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.equal_to_zero_i ( alu_is_equal_result ),
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.data_ind_timing_i ( data_ind_timing_i ),
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.imd_val_q_i ( imd_val_q_i ),
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.imd_val_d_o ( multdiv_imd_val_d ),
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.imd_val_we_o ( multdiv_imd_val_we ),
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.multdiv_ready_id_i ( multdiv_ready_id_i ),
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.valid_o ( multdiv_valid ),
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.multdiv_result_o ( multdiv_result )
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);
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end
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// Multiplier/divider may require multiple cycles. The ALU output is valid in the same cycle
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// unless the intermediate result register is being written (which indicates this isn't the
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// final cycle of ALU operation).
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assign ex_valid_o = multdiv_sel ? multdiv_valid : ~(|alu_imd_val_we);
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endmodule
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