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4b01580a7b
- The prefetch buffer needs to know when space is available in the fetch FIFO to accept a new external request. - This change updates that logic to look at what is in the FIFO and what is outstanding on the bus to decide when space is available rather than always assuming the maximum number of requests are outstanding. - This improves the usage efficiency of the FIFO and fixes #574 Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
243 lines
8.9 KiB
Systemverilog
243 lines
8.9 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Fetch Fifo for 32 bit memory interface
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*
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* input port: send address and data to the FIFO
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* clear_i clears the FIFO for the following cycle, including any new request
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*/
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`include "prim_assert.sv"
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module ibex_fetch_fifo #(
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parameter int unsigned NUM_REQS = 2
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) (
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input logic clk_i,
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input logic rst_ni,
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// control signals
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input logic clear_i, // clears the contents of the FIFO
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output logic [NUM_REQS-1:0] busy_o,
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// input port
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input logic in_valid_i,
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input logic [31:0] in_addr_i,
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input logic [31:0] in_rdata_i,
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input logic in_err_i,
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// output port
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output logic out_valid_o,
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input logic out_ready_i,
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output logic [31:0] out_addr_o,
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output logic [31:0] out_rdata_o,
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output logic out_err_o,
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output logic out_err_plus2_o
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);
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localparam int unsigned DEPTH = NUM_REQS+1;
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// index 0 is used for output
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logic [DEPTH-1:0] [31:0] rdata_d, rdata_q;
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logic [DEPTH-1:0] err_d, err_q;
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logic [DEPTH-1:0] valid_d, valid_q;
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logic [DEPTH-1:0] lowest_free_entry;
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logic [DEPTH-1:0] valid_pushed, valid_popped;
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logic [DEPTH-1:0] entry_en;
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logic pop_fifo;
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logic [31:0] rdata, rdata_unaligned;
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logic err, err_unaligned, err_plus2;
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logic valid, valid_unaligned;
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logic aligned_is_compressed, unaligned_is_compressed;
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logic addr_incr_two;
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logic [31:1] instr_addr_d, instr_addr_q;
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logic instr_addr_en;
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logic unused_addr_in;
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/////////////////
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// Output port //
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/////////////////
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assign rdata = valid_q[0] ? rdata_q[0] : in_rdata_i;
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assign err = valid_q[0] ? err_q[0] : in_err_i;
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assign valid = valid_q[0] | in_valid_i;
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// The FIFO contains word aligned memory fetches, but the instructions contained in each entry
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// might be half-word aligned (due to compressed instructions)
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// e.g.
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// | 31 16 | 15 0 |
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// FIFO entry 0 | Instr 1 [15:0] | Instr 0 [15:0] |
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// FIFO entry 1 | Instr 2 [15:0] | Instr 1 [31:16] |
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//
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// The FIFO also has a direct bypass path, so a complete instruction might be made up of data
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// from the FIFO and new incoming data.
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//
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// Construct the output data for an unaligned instruction
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assign rdata_unaligned = valid_q[1] ? {rdata_q[1][15:0], rdata[31:16]} :
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{in_rdata_i[15:0], rdata[31:16]};
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// If entry[1] is valid, an error can come from entry[0] or entry[1], unless the
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// instruction in entry[0] is compressed (entry[1] is a new instruction)
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// If entry[1] is not valid, and entry[0] is, an error can come from entry[0] or the incoming
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// data, unless the instruction in entry[0] is compressed
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// If entry[0] is not valid, the error must come from the incoming data
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assign err_unaligned = valid_q[1] ? ((err_q[1] & ~unaligned_is_compressed) | err_q[0]) :
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((valid_q[0] & err_q[0]) |
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(in_err_i & (~valid_q[0] | ~unaligned_is_compressed)));
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// Record when an error is caused by the second half of an unaligned 32bit instruction.
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// Only needs to be correct when unaligned and if err_unaligned is set
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assign err_plus2 = valid_q[1] ? (err_q[1] & ~err_q[0]) :
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(in_err_i & valid_q[0] & ~err_q[0]);
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// An uncompressed unaligned instruction is only valid if both parts are available
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assign valid_unaligned = valid_q[1] ? 1'b1 :
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(valid_q[0] & in_valid_i);
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// If there is an error, rdata is unknown
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assign unaligned_is_compressed = (rdata[17:16] != 2'b11) | err;
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assign aligned_is_compressed = (rdata[ 1: 0] != 2'b11) & ~err;
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////////////////////////////////////////
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// Instruction aligner (if unaligned) //
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////////////////////////////////////////
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always_comb begin
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if (out_addr_o[1]) begin
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// unaligned case
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out_rdata_o = rdata_unaligned;
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out_err_o = err_unaligned;
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out_err_plus2_o = err_plus2;
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if (unaligned_is_compressed) begin
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out_valid_o = valid;
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end else begin
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out_valid_o = valid_unaligned;
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end
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end else begin
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// aligned case
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out_rdata_o = rdata;
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out_err_o = err;
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out_err_plus2_o = 1'b0;
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out_valid_o = valid;
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end
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end
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/////////////////////////
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// Instruction address //
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/////////////////////////
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// Update the address on branches and every time an instruction is driven
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assign instr_addr_en = clear_i | (out_ready_i & out_valid_o);
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// Increment the address by two every time a compressed instruction is popped
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assign addr_incr_two = instr_addr_q[1] ? unaligned_is_compressed :
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aligned_is_compressed;
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assign instr_addr_d = clear_i ? in_addr_i[31:1] :
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(instr_addr_q[31:1] +
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// Increment address by 4 or 2
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{29'd0,~addr_incr_two,addr_incr_two});
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always_ff @(posedge clk_i) begin
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if (instr_addr_en) begin
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instr_addr_q <= instr_addr_d;
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end
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end
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assign out_addr_o[31:1] = instr_addr_q[31:1];
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assign out_addr_o[0] = 1'b0;
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// The LSB of the address is unused, since all addresses are halfword aligned
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assign unused_addr_in = in_addr_i[0];
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/////////////////
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// FIFO status //
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/////////////////
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// Indicate the fill level of fifo-entries. This is used to determine when a new request can be
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// made on the bus. The prefetch buffer only needs to know about the upper entries which overlap
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// with NUM_REQS.
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assign busy_o = valid_q[DEPTH-1:DEPTH-NUM_REQS];
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/////////////////////
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// FIFO management //
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/////////////////////
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// Since an entry can contain unaligned instructions, popping an entry can leave the entry valid
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assign pop_fifo = out_ready_i & out_valid_o & (~aligned_is_compressed | out_addr_o[1]);
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for (genvar i = 0; i < (DEPTH - 1); i++) begin : g_fifo_next
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// Calculate lowest free entry (write pointer)
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if (i == 0) begin : g_ent0
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assign lowest_free_entry[i] = ~valid_q[i];
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end else begin : g_ent_others
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assign lowest_free_entry[i] = ~valid_q[i] & valid_q[i-1];
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end
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// An entry is set when an incoming request chooses the lowest available entry
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assign valid_pushed[i] = (in_valid_i & lowest_free_entry[i]) |
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valid_q[i];
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// Popping the FIFO shifts all entries down
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assign valid_popped[i] = pop_fifo ? valid_pushed[i+1] : valid_pushed[i];
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// All entries are wiped out on a clear
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assign valid_d[i] = valid_popped[i] & ~clear_i;
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// data flops are enabled if there is new data to shift into it, or
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assign entry_en[i] = (valid_pushed[i+1] & pop_fifo) |
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// a new request is incoming and this is the lowest free entry
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(in_valid_i & lowest_free_entry[i] & ~pop_fifo);
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// take the next entry or the incoming data
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assign rdata_d[i] = valid_q[i+1] ? rdata_q[i+1] : in_rdata_i;
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assign err_d [i] = valid_q[i+1] ? err_q [i+1] : in_err_i;
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end
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// The top entry is similar but with simpler muxing
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assign lowest_free_entry[DEPTH-1] = ~valid_q[DEPTH-1] & valid_q[DEPTH-2];
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assign valid_pushed [DEPTH-1] = valid_q[DEPTH-1] | (in_valid_i & lowest_free_entry[DEPTH-1]);
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assign valid_popped [DEPTH-1] = pop_fifo ? 1'b0 : valid_pushed[DEPTH-1];
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assign valid_d [DEPTH-1] = valid_popped[DEPTH-1] & ~clear_i;
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assign entry_en[DEPTH-1] = in_valid_i & lowest_free_entry[DEPTH-1];
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assign rdata_d [DEPTH-1] = in_rdata_i;
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assign err_d [DEPTH-1] = in_err_i;
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////////////////////
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// FIFO registers //
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////////////////////
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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valid_q <= '0;
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end else begin
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valid_q <= valid_d;
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end
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end
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for (genvar i = 0; i < DEPTH; i++) begin : g_fifo_regs
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always_ff @(posedge clk_i) begin
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if (entry_en[i]) begin
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rdata_q[i] <= rdata_d[i];
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err_q[i] <= err_d[i];
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end
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end
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end
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////////////////
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// Assertions //
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////////////////
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// Must not push and pop simultaneously when FIFO full.
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`ASSERT(IbexFetchFifoPushPopFull,
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(in_valid_i && pop_fifo) |-> (!valid_q[DEPTH-1] || clear_i))
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// Must not push to FIFO when full.
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`ASSERT(IbexFetchFifoPushFull,
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(in_valid_i) |-> (!valid_q[DEPTH-1] || clear_i))
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endmodule
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