mirror of
https://github.com/lowRISC/ibex.git
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500 lines
11 KiB
Systemverilog
500 lines
11 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Package with constants used by Ibex
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*/
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package ibex_pkg;
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/////////////////////////
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// RV32B Paramter Enum //
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/////////////////////////
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typedef enum integer {
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RV32BNone,
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RV32BBalanced,
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RV32BFull
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} rv32b_e;
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/////////////
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// Opcodes //
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/////////////
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typedef enum logic [6:0] {
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OPCODE_LOAD = 7'h03,
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OPCODE_PA = 7'h0b,
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OPCODE_MISC_MEM = 7'h0f,
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OPCODE_OP_IMM = 7'h13,
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OPCODE_AUIPC = 7'h17,
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OPCODE_STORE = 7'h23,
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OPCODE_OP = 7'h33,
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OPCODE_LUI = 7'h37,
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OPCODE_BRANCH = 7'h63,
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OPCODE_JALR = 7'h67,
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OPCODE_JAL = 7'h6f,
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OPCODE_SYSTEM = 7'h73
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} opcode_e;
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////////////////////
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// ALU operations //
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////////////////////
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typedef enum logic [5:0] {
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// Arithmetics
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ALU_ADD,
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ALU_SUB,
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// Logics
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ALU_XOR,
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ALU_OR,
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ALU_AND,
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// RV32B
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ALU_XNOR,
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ALU_ORN,
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ALU_ANDN,
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// Shifts
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ALU_SRA,
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ALU_SRL,
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ALU_SLL,
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// RV32B
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ALU_SRO,
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ALU_SLO,
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ALU_ROR,
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ALU_ROL,
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ALU_GREV,
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ALU_GORC,
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ALU_SHFL,
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ALU_UNSHFL,
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// Comparisons
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ALU_LT,
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ALU_LTU,
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ALU_GE,
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ALU_GEU,
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ALU_EQ,
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ALU_NE,
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// RV32B
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ALU_MIN,
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ALU_MINU,
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ALU_MAX,
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ALU_MAXU,
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// Pack
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// RV32B
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ALU_PACK,
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ALU_PACKU,
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ALU_PACKH,
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// Sign-Extend
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// RV32B
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ALU_SEXTB,
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ALU_SEXTH,
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// Bitcounting
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// RV32B
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ALU_CLZ,
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ALU_CTZ,
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ALU_PCNT,
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// Set lower than
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ALU_SLT,
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ALU_SLTU,
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// Ternary Bitmanip Operations
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// RV32B
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ALU_CMOV,
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ALU_CMIX,
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ALU_FSL,
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ALU_FSR,
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// Single-Bit Operations
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// RV32B
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ALU_SBSET,
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ALU_SBCLR,
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ALU_SBINV,
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ALU_SBEXT,
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// Bit Extract / Deposit
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// RV32B
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ALU_BEXT,
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ALU_BDEP,
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// Bit Field Place
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// RV32B
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ALU_BFP,
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// Carry-less Multiply
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// RV32B
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ALU_CLMUL,
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ALU_CLMULR,
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ALU_CLMULH,
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// Cyclic Redundancy Check
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ALU_CRC32_B,
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ALU_CRC32C_B,
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ALU_CRC32_H,
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ALU_CRC32C_H,
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ALU_CRC32_W,
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ALU_CRC32C_W
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} alu_op_e;
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typedef enum logic [1:0] {
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// Multiplier/divider
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MD_OP_MULL,
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MD_OP_MULH,
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MD_OP_DIV,
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MD_OP_REM
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} md_op_e;
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//////////////////////////////////
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// Control and status registers //
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//////////////////////////////////
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// CSR operations
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typedef enum logic [1:0] {
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CSR_OP_READ,
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CSR_OP_WRITE,
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CSR_OP_SET,
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CSR_OP_CLEAR
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} csr_op_e;
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// Privileged mode
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typedef enum logic[1:0] {
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PRIV_LVL_M = 2'b11,
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PRIV_LVL_H = 2'b10,
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PRIV_LVL_S = 2'b01,
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PRIV_LVL_U = 2'b00
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} priv_lvl_e;
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// Constants for the dcsr.xdebugver fields
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typedef enum logic[3:0] {
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XDEBUGVER_NO = 4'd0, // no external debug support
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XDEBUGVER_STD = 4'd4, // external debug according to RISC-V debug spec
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XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec
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} x_debug_ver_e;
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//////////////
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// WB stage //
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//////////////
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// Type of instruction present in writeback stage
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typedef enum logic[1:0] {
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WB_INSTR_LOAD, // Instruction is awaiting load data
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WB_INSTR_STORE, // Instruction is awaiting store response
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WB_INSTR_OTHER // Instruction doesn't fit into above categories
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} wb_instr_type_e;
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//////////////
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// ID stage //
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//////////////
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// Operand a selection
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typedef enum logic[1:0] {
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OP_A_REG_A,
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OP_A_FWD,
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OP_A_CURRPC,
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OP_A_IMM
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} op_a_sel_e;
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// Immediate a selection
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typedef enum logic {
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IMM_A_Z,
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IMM_A_ZERO
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} imm_a_sel_e;
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// Operand b selection
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typedef enum logic {
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OP_B_REG_B,
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OP_B_IMM
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} op_b_sel_e;
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// Immediate b selection
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typedef enum logic [2:0] {
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IMM_B_I,
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IMM_B_S,
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IMM_B_B,
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IMM_B_U,
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IMM_B_J,
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IMM_B_INCR_PC,
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IMM_B_INCR_ADDR
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} imm_b_sel_e;
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// Regfile write data selection
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typedef enum logic [1:0] {
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RF_WD_EX,
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RF_WD_CSR,
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RF_WD_PA
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} rf_wd_sel_e;
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//////////////
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// IF stage //
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//////////////
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// PC mux selection
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typedef enum logic [2:0] {
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PC_BOOT,
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PC_JUMP,
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PC_EXC,
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PC_ERET,
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PC_DRET
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} pc_sel_e;
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// Exception PC mux selection
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typedef enum logic [1:0] {
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EXC_PC_EXC,
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EXC_PC_IRQ,
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EXC_PC_DBD,
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EXC_PC_DBG_EXC // Exception while in debug mode
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} exc_pc_sel_e;
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// Interrupt requests
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typedef struct packed {
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logic irq_software;
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logic irq_timer;
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logic irq_external;
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logic [14:0] irq_fast; // 15 fast interrupts,
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// one interrupt is reserved for NMI (not visible through mip/mie)
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} irqs_t;
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// Exception cause
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typedef enum logic [5:0] {
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EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd03},
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EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd07},
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EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11},
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// EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16},
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// EXC_CAUSE_IRQ_FAST_14 = {1'b1, 5'd30},
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EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}, // == EXC_CAUSE_IRQ_FAST_15
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EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd00},
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EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd01},
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EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd02},
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EXC_CAUSE_BREAKPOINT = {1'b0, 5'd03},
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EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd05},
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EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd07},
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EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd08},
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EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}
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} exc_cause_e;
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// Debug cause
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typedef enum logic [2:0] {
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DBG_CAUSE_NONE = 3'h0,
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DBG_CAUSE_EBREAK = 3'h1,
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DBG_CAUSE_TRIGGER = 3'h2,
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DBG_CAUSE_HALTREQ = 3'h3,
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DBG_CAUSE_STEP = 3'h4
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} dbg_cause_e;
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// PMP constants
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parameter int unsigned PMP_MAX_REGIONS = 16;
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parameter int unsigned PMP_CFG_W = 8;
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// PMP acces type
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parameter int unsigned PMP_I = 0;
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parameter int unsigned PMP_D = 1;
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typedef enum logic [1:0] {
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PMP_ACC_EXEC = 2'b00,
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PMP_ACC_WRITE = 2'b01,
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PMP_ACC_READ = 2'b10
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} pmp_req_e;
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// PMP cfg structures
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typedef enum logic [1:0] {
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PMP_MODE_OFF = 2'b00,
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PMP_MODE_TOR = 2'b01,
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PMP_MODE_NA4 = 2'b10,
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PMP_MODE_NAPOT = 2'b11
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} pmp_cfg_mode_e;
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typedef struct packed {
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logic lock;
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pmp_cfg_mode_e mode;
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logic exec;
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logic write;
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logic read;
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} pmp_cfg_t;
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// CSRs
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typedef enum logic[11:0] {
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// Machine information
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CSR_MHARTID = 12'hF14,
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// Machine trap setup
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CSR_MSTATUS = 12'h300,
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CSR_MISA = 12'h301,
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CSR_MIE = 12'h304,
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CSR_MTVEC = 12'h305,
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// Machine trap handling
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CSR_MSCRATCH = 12'h340,
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CSR_MEPC = 12'h341,
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CSR_MCAUSE = 12'h342,
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CSR_MTVAL = 12'h343,
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CSR_MIP = 12'h344,
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// Physical memory protection
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CSR_PMPCFG0 = 12'h3A0,
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CSR_PMPCFG1 = 12'h3A1,
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CSR_PMPCFG2 = 12'h3A2,
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CSR_PMPCFG3 = 12'h3A3,
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CSR_PMPADDR0 = 12'h3B0,
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CSR_PMPADDR1 = 12'h3B1,
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CSR_PMPADDR2 = 12'h3B2,
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CSR_PMPADDR3 = 12'h3B3,
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CSR_PMPADDR4 = 12'h3B4,
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CSR_PMPADDR5 = 12'h3B5,
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CSR_PMPADDR6 = 12'h3B6,
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CSR_PMPADDR7 = 12'h3B7,
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CSR_PMPADDR8 = 12'h3B8,
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CSR_PMPADDR9 = 12'h3B9,
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CSR_PMPADDR10 = 12'h3BA,
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CSR_PMPADDR11 = 12'h3BB,
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CSR_PMPADDR12 = 12'h3BC,
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CSR_PMPADDR13 = 12'h3BD,
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CSR_PMPADDR14 = 12'h3BE,
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CSR_PMPADDR15 = 12'h3BF,
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// Debug trigger
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CSR_TSELECT = 12'h7A0,
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CSR_TDATA1 = 12'h7A1,
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CSR_TDATA2 = 12'h7A2,
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CSR_TDATA3 = 12'h7A3,
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CSR_MCONTEXT = 12'h7A8,
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CSR_SCONTEXT = 12'h7AA,
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// Debug/trace
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CSR_DCSR = 12'h7b0,
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CSR_DPC = 12'h7b1,
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// Debug
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CSR_DSCRATCH0 = 12'h7b2, // optional
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CSR_DSCRATCH1 = 12'h7b3, // optional
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// Machine Counter/Timers
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CSR_MCOUNTINHIBIT = 12'h320,
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CSR_MHPMEVENT3 = 12'h323,
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CSR_MHPMEVENT4 = 12'h324,
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CSR_MHPMEVENT5 = 12'h325,
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CSR_MHPMEVENT6 = 12'h326,
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CSR_MHPMEVENT7 = 12'h327,
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CSR_MHPMEVENT8 = 12'h328,
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CSR_MHPMEVENT9 = 12'h329,
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CSR_MHPMEVENT10 = 12'h32A,
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CSR_MHPMEVENT11 = 12'h32B,
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CSR_MHPMEVENT12 = 12'h32C,
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CSR_MHPMEVENT13 = 12'h32D,
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CSR_MHPMEVENT14 = 12'h32E,
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CSR_MHPMEVENT15 = 12'h32F,
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CSR_MHPMEVENT16 = 12'h330,
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CSR_MHPMEVENT17 = 12'h331,
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CSR_MHPMEVENT18 = 12'h332,
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CSR_MHPMEVENT19 = 12'h333,
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CSR_MHPMEVENT20 = 12'h334,
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CSR_MHPMEVENT21 = 12'h335,
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CSR_MHPMEVENT22 = 12'h336,
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CSR_MHPMEVENT23 = 12'h337,
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CSR_MHPMEVENT24 = 12'h338,
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CSR_MHPMEVENT25 = 12'h339,
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CSR_MHPMEVENT26 = 12'h33A,
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CSR_MHPMEVENT27 = 12'h33B,
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CSR_MHPMEVENT28 = 12'h33C,
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CSR_MHPMEVENT29 = 12'h33D,
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CSR_MHPMEVENT30 = 12'h33E,
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CSR_MHPMEVENT31 = 12'h33F,
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CSR_MCYCLE = 12'hB00,
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CSR_MINSTRET = 12'hB02,
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CSR_MHPMCOUNTER3 = 12'hB03,
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CSR_MHPMCOUNTER4 = 12'hB04,
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CSR_MHPMCOUNTER5 = 12'hB05,
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CSR_MHPMCOUNTER6 = 12'hB06,
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CSR_MHPMCOUNTER7 = 12'hB07,
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CSR_MHPMCOUNTER8 = 12'hB08,
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CSR_MHPMCOUNTER9 = 12'hB09,
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CSR_MHPMCOUNTER10 = 12'hB0A,
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CSR_MHPMCOUNTER11 = 12'hB0B,
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CSR_MHPMCOUNTER12 = 12'hB0C,
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CSR_MHPMCOUNTER13 = 12'hB0D,
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CSR_MHPMCOUNTER14 = 12'hB0E,
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CSR_MHPMCOUNTER15 = 12'hB0F,
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CSR_MHPMCOUNTER16 = 12'hB10,
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CSR_MHPMCOUNTER17 = 12'hB11,
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CSR_MHPMCOUNTER18 = 12'hB12,
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CSR_MHPMCOUNTER19 = 12'hB13,
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CSR_MHPMCOUNTER20 = 12'hB14,
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CSR_MHPMCOUNTER21 = 12'hB15,
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CSR_MHPMCOUNTER22 = 12'hB16,
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CSR_MHPMCOUNTER23 = 12'hB17,
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CSR_MHPMCOUNTER24 = 12'hB18,
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CSR_MHPMCOUNTER25 = 12'hB19,
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CSR_MHPMCOUNTER26 = 12'hB1A,
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CSR_MHPMCOUNTER27 = 12'hB1B,
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CSR_MHPMCOUNTER28 = 12'hB1C,
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CSR_MHPMCOUNTER29 = 12'hB1D,
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CSR_MHPMCOUNTER30 = 12'hB1E,
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CSR_MHPMCOUNTER31 = 12'hB1F,
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CSR_MCYCLEH = 12'hB80,
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CSR_MINSTRETH = 12'hB82,
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CSR_MHPMCOUNTER3H = 12'hB83,
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CSR_MHPMCOUNTER4H = 12'hB84,
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CSR_MHPMCOUNTER5H = 12'hB85,
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CSR_MHPMCOUNTER6H = 12'hB86,
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CSR_MHPMCOUNTER7H = 12'hB87,
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CSR_MHPMCOUNTER8H = 12'hB88,
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CSR_MHPMCOUNTER9H = 12'hB89,
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CSR_MHPMCOUNTER10H = 12'hB8A,
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CSR_MHPMCOUNTER11H = 12'hB8B,
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CSR_MHPMCOUNTER12H = 12'hB8C,
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CSR_MHPMCOUNTER13H = 12'hB8D,
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CSR_MHPMCOUNTER14H = 12'hB8E,
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CSR_MHPMCOUNTER15H = 12'hB8F,
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CSR_MHPMCOUNTER16H = 12'hB90,
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CSR_MHPMCOUNTER17H = 12'hB91,
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CSR_MHPMCOUNTER18H = 12'hB92,
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CSR_MHPMCOUNTER19H = 12'hB93,
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CSR_MHPMCOUNTER20H = 12'hB94,
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CSR_MHPMCOUNTER21H = 12'hB95,
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CSR_MHPMCOUNTER22H = 12'hB96,
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CSR_MHPMCOUNTER23H = 12'hB97,
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CSR_MHPMCOUNTER24H = 12'hB98,
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CSR_MHPMCOUNTER25H = 12'hB99,
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CSR_MHPMCOUNTER26H = 12'hB9A,
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CSR_MHPMCOUNTER27H = 12'hB9B,
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CSR_MHPMCOUNTER28H = 12'hB9C,
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CSR_MHPMCOUNTER29H = 12'hB9D,
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CSR_MHPMCOUNTER30H = 12'hB9E,
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CSR_MHPMCOUNTER31H = 12'hB9F,
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CSR_CPUCTRL = 12'h7C0,
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CSR_SECURESEED = 12'h7C1,
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CSR_PAKEY0 = 12'h7C2,
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CSR_PAKEY1 = 12'h7C3,
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CSR_PAKEY2 = 12'h7C4,
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CSR_PAKEY3 = 12'h7C5
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} csr_num_e;
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// CSR pmp-related offsets
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parameter logic [11:0] CSR_OFF_PMP_CFG = 12'h3A0; // pmp_cfg @ 12'h3a0 - 12'h3a3
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parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf
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// CSR status bits
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parameter int unsigned CSR_MSTATUS_MIE_BIT = 3;
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parameter int unsigned CSR_MSTATUS_MPIE_BIT = 7;
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parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW = 11;
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parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;
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parameter int unsigned CSR_MSTATUS_MPRV_BIT = 17;
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parameter int unsigned CSR_MSTATUS_TW_BIT = 21;
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// CSR machine ISA
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parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32
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// CSR interrupt pending/enable bits
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parameter int unsigned CSR_MSIX_BIT = 3;
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parameter int unsigned CSR_MTIX_BIT = 7;
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parameter int unsigned CSR_MEIX_BIT = 11;
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parameter int unsigned CSR_MFIX_BIT_LOW = 16;
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parameter int unsigned CSR_MFIX_BIT_HIGH = 30;
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endpackage
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