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8e9a621f67
Before we changed to vendoring in our RAM primitives from OpenTitan, there was an SRAM_INIT_FILE define that you could stick in your core file. That's now gone away, replaced by a parameter (MemInitFile). If we want to plumb that in, we need to pass it properly through the wrappers.
68 lines
1.7 KiB
Systemverilog
68 lines
1.7 KiB
Systemverilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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/**
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* Single-port RAM with 1 cycle read/write delay, 32 bit words
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*/
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`include "prim_assert.sv"
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module ram_1p #(
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parameter int Depth = 128,
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parameter MemInitFile = ""
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) (
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input clk_i,
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input rst_ni,
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input req_i,
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input we_i,
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input [ 3:0] be_i,
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input [31:0] addr_i,
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input [31:0] wdata_i,
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output logic rvalid_o,
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output logic [31:0] rdata_o
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);
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localparam int Aw = $clog2(Depth);
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logic [Aw-1:0] addr_idx;
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assign addr_idx = addr_i[Aw-1+2:2];
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logic [31-Aw:0] unused_addr_parts;
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assign unused_addr_parts = {addr_i[31:Aw+2], addr_i[1:0]};
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// Convert byte mask to SRAM bit mask.
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logic [31:0] wmask;
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always_comb begin
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for (int i = 0 ; i < 4 ; i++) begin
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// mask for read data
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wmask[8*i+:8] = {8{be_i[i]}};
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end
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end
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// |rvalid| in the bus module is an "ack" (which is a different meaning than
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// in the prim_ram_*_adv modules). prim_ram_1p is guaranteed to return data
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// in the next cycle.
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always_ff @(posedge clk_i, negedge rst_ni) begin
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if (!rst_ni) begin
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rvalid_o <= 1'b0;
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end else begin
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rvalid_o <= req_i;
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end
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end
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prim_ram_1p #(
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.Width(32),
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.DataBitsPerMask(8),
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.Depth(Depth),
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.MemInitFile(MemInitFile)
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) u_ram (
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.clk_i (clk_i),
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.req_i (req_i),
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.write_i (we_i),
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.wmask_i (wmask),
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.addr_i (addr_idx),
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.wdata_i (wdata_i),
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.rdata_o (rdata_o)
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);
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endmodule
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