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79bb6c7832
Adds significant functionality to synthesis flow. Timing reports are generated using OpenSTA and an area report is generated. Flow supports open Nangate45 library from OpenROAD.
16 lines
356 B
Verilog
16 lines
356 B
Verilog
// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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// Dummy clock gating module without the clock gate for yosys synthesis
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module prim_clock_gating (
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input clk_i,
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input en_i,
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input test_en_i,
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output clk_o
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);
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assign clk_o = clk_i;
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endmodule
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